LM2759SDEV datasheet(10/22 Pages) TI1

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SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

SDA

SCL

STO

condition

START condition

LM2759

SNVS577D – JUNE 2008 – REVISED MAY 2013

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I2C COMPATIBLE INTERFACE

START AND STOP CONDITIONS

START and STOP conditions classify the beginning and the end of the I2C session. A START condition is

defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as

the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and

STOP conditions. The I2C bus is considered to be busy after a START condition and free after a STOP condition.

During data transmission, the I2C master can generate repeated START conditions. First START and repeated

START conditions are equivalent, function-wise.

Figure 15. Start and Stop Conditions

DATA VALIDITY

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when SCL is LOW.

Figure 16. Data Validity Diagram

A pull-up resistor between the controller's VIO line and SDA must be greater than [(VIO-VOL) / 3.5mA] to meet

the VOL requirement on SDA. Using a larger pull-up resistor results in lower switching current with slower edges,

while using a smaller pull-up results in higher switching currents with faster edges.

TRANSFERING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each

byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the

master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM2759 pulls down

the SDA line during the 9th clock pulse, signifying an acknowledge. The LM2759 generates an acknowledge

after each byte is received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). The LM2759 address is 53h. For the eighth bit, a “0” indicates a

WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The

third byte contains data to write to the selected register.

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