L99MD02 datasheet(11/46 Pages) STMICROELECTRONICS

11 / 46 page

L99MD02

Pin definitions and functions

Doc ID 16082 Rev 5

11/46

Pin definitions and functions

Table 3.

Pin description

Symbol

Function

1, 18, 19, 36

PGND

Power ground: reference potential

AGND

Analog ground: reference potential

DGND

Digital ground: reference potential

6, 10, 13, 21,

23, 25, 32, 34

N.C.

Not connected

Exposed pad: reference potential connected to PGND

2, 3, 16, 17, 20,

OUT 1 -6

Half bridge-output: the output is built by a high-side and a low-side

switch, which are internally connected. The output stage of both

switches is a power DMOS transistor. Each driver has an internal

parasitic reverse diode (bulk-drain-diode: high-side driver from output

to VSx, low-side driver from PGND to output).

VCC

Logic voltage supply 3.3V / 5V for this input a ceramic capacitor as

close as possible to GND is recommended

4, 5, 33

VSA

Power supply voltage for OUT 1 to 3 (external reverse protection

required): for this input a ceramic capacitor as close as possible to

GND is recommended. Important: For the capability of driving the full

current at the outputs all pins of VSA must be externally connected!

14, 15, 22

VSB

Power supply voltage for OUT 4 to 6 (external reverse protection

required): for this input a ceramic capacitor as close as possible to

GND is recommended. Important: For the capability of driving the full

current at the outputs all pins of VSB must be externally connected!

VS supply and monitoring

7, 8

CURR1 / 2 Current monitor 1 / 2

Enable enable the L99MD02

SPI data in the input requires CMOS logic levels and receives serial

data from the microcontroller. The data is a 24 bit control word and the

most significant bit (MSB) is transferred first.

SPI data out the diagnosis data is available via the SPI and this 3-

state output. The output will remain in 3-state, if the chip is not

selected by the input CSN (CSN = high)

CSN

SPI CSN chip select not (active low) this input is low active and

requires CMOS logic levels. The serial data transfer between the

L99MD02 and micro controller is enabled by pulling the input CSN to

low level.

SCK

SPI serial clock input this input controls the internal shift register of the

SPI and requires CMOS logic levels.

L99MD02 Datasheet(PDF) 11 Page - STMicroelectronics

L99MD02 Datasheet(HTML) 11 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL