Copyright 1998 National Semiconductor Corp.

4

www.national.com

2.0 Pin Description

Table 1:

Pin Description

PIN NAME

TYPE

DESCRIPTION

SCLK

1

5

OUTPUT (slope controlled). CR16A bus interface System CLocK output.

Vdd

2

Digital supply voltage

Vss

3

Digital ground.

4-11

5

TRI-STATE OUTPUT. Power Down pins 7 to 0. PD7,6 have 12 mA drive.

RFCLK

12

5b

OUTPUT (Slope controlled). 10 MHz clock output. Logic ‘0’ after reset or when dis-

abled.

MEN1n

13

5

OUTPUT. Load Enable. Can be synchronized to LKD input

SO

14

1

TRI-STATE OUTPUT. Serial data output.

SK

15

5

OUTPUT. Serial interface clock: 1.152 MHz

LKD

16

1

INPUT. LocK Detect input for synchronisation purposes.

RDI

17

analog

INPUT. Received Data. It is programmable to invert this input.

CMPREF

18

analog

INPUT. Comparator reference level. Internally a six bit DAC can be connected to

this pin to compensate for DC offsets.

RSSI

19

analog

INPUT. 6-bit ADC input with peak hold circuitry. Activated on PD0 = low. If PD0 =

high the RSSI input will be discharged to ground.

AVD

20

Analog supply voltage

AVS

21

Analog ground

TDO

22

5/analog

TRI-STATE OUTPUT. Transmit Data. Can be programmed to be inverted.

P0[0] or

UTX

23

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. UART data output.

P0[1] or

URX

24

3

INPUT/OUTPUT with selectable pull down resistor. General purpose memory

mapped I/O port bit. UART data input.

P0[2]

25

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. Can be switched to ADPCM/CODEC testpoints.

P0[3]

26

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit.Can be switched to ADPCM/CODEC testpoints.

P0[4]

27

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. Can be switched to ADPCM/CODEC testpoints.

P0[5]

28

3

INPUT/OUTPUT with selectable pull down resistor. General purpose memory

mapped I/O port bit. Can be switched to ADPCM/CODEC testpoints.

P0[6]

29

3

INPUT/OUTPUT with selectable pull down resistor. General purpose memory

mapped I/O port bit. Can be switched to ADPCM/CODEC testpoints.

P0[7]

30

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. Can be switched to ADPCM/CODEC testpoints.

P1[0]

31

2

INPUT/OUTPUT with selectable pull up resistor and 12 mA drive current. General

purpose memory mapped I/O port bit. Can be programmed to generate an internal

interrupt.

P1[1]

32

2

INPUT/OUTPUT with selectable pull up resistor and 12 mA drive current. General

purpose memory mapped I/O port bit. Can be programmed to generate an internal

interrupt.

P1[2]

33

2

INPUT/OUTPUT with selectable pull up resistor and 12 mA drive current. General

purpose memory mapped I/O port bit. Can be programmed to generate an internal

interrupt.

P1[3]

34

2

INPUT/OUTPUT with selectable pull up resistor and 12 mA drive current. General

purpose memory mapped I/O port bit. Can be programmed to generate an internal

interrupt.

P1[4]

35

2

INPUT/OUTPUT with selectable pull up resistor and 12 mA drive current. General

purpose memory mapped I/O port bit. Can be programmed to generate an internal

interrupt.