Copyright 1998 National Semiconductor Corp.

6

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NOTE:

All digital outputs can sink/source 2 mA unless otherwise specified. All digital inputs are Schmitt trigger

types. After reset all I/Os are set to input and all pull-up or pull-down resistors are enabled. The p0[0] pull-

up resistor is disabled at start-up.

RSTn

68

1

INPUT. Active low Reset.

HOLDn

or MI

69

2

INPUT/OUTPUT with fixed pull up. Selects HOLD mode. If set to ‘0’, the CR16A

processor will terminate its current instruction and the ADx, WRN, RDN will go TRI-

STATE. In this mode an external CR16A can control the SC14422 completely.

In Emulation mode MI output is automatically selected. Then this pin goes high if

an internal interrupt is asserted. In core mode this pin is a maskable interrupt input

MI to the CR16A core.

ACSn

70

5

OUTPUT. Auxiliary Chip Select not. This signal becomes low if the address range

is within the programmed address range.

AD3..0

71-74

1

OUTPUT. Address bit 3 to 0. In HOLD mode these pins are input.

DAB7..0

82-75

1

INPUT/OUTPUT. Data bus bit 7..0

RCSn

83

5

OUTPUT. ROM Chip Select not. Low active if none of the internal peripherals or the

ACSn is addressed.

AD10

84

1

OUTPUT. Address bit 10. In HOLD mode this pin is input.

RDn

85

1

OUTPUT. Active low read. In HOLD mode this pin is input.

AD11

86

1

OUTPUT. Address bit 11. In HOLD mode this pin is input.

AD9

87

1

OUTPUT. Address bit 9. In HOLD mode this pin is input.

AD8

88

1

OUTPUT. Address bit 8. In HOLD mode this pin is input.

AD13

89

1

OUTPUT. Address bit 13. In HOLD mode this pin is input.

AD14

90

1

OUTPUT. Address bit 14. In HOLD mode this pin is input.

AD17

91

1

OUTPUT. Address bit 17. In HOLD mode this pin is output.

WRn

92

1

OUTPUT. Active low write signal. In HOLD mode this pin is input.

AD16,15, 12

93-95

1

OUTPUT. Address bit 16,15 & 12. In HOLD mode these pins are input.

AD7-4

96-99

1

OUTPUT. Address bit 7 to 4. In HOLD mode these pins are input.

CLK1M

100

1

OUTPUT. Fixed bit clock output (1.152Mhz). Synchronized to the DECT bit clock.

Will be logic ‘0’ if the DECT Dedicated Instruction Processor (DIP) is frozen.

Will be logic ‘1’ after a hardware reset (RSTN) or software reset (DEBUG_REG[1]).

Table 1:

Pin Description)

PIN NAME

NR

TYPE

DESCRIPTION