TMS45160, TMS45160P

262144-WORD BY 16-BIT HIGH-SPEED

DYNAMIC RANDOM-ACCESS MEMORIES

SMHS160D – AUGUST 1992 – REVISED JUNE 1995

13

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

RAS

UCAS

LCAS

A0 – A8

W

DQ0 – DQ15

OE

tWC

tRAS

tT

tRCD

tCSH

tCRP

tRP

tCP

tASR

tRAD

tRAH

tASC

tCAL

tRAL

tCAH

tAR

tWCS

tWCH

tRWL

tWP

tDHR

tDH

tDS

Valid Data In

Row Address

Column

Address

tCAS

tRSH

tCWL

tCLCH

(see Note A)

tWCR

Don’t Care

Don’t Care

Don’t Care

Don’t Care

Don’t Care

Don’t Care

NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.

B. xCAS order is arbitrary.

Figure 4. Early-Write-Cycle Timing