VIPER53DIP datasheet(18/24 Pages) STMICROELECTRONICS

18 / 24 page

VIPer53DIP / VIPer53SP

18/24

in the current mode section. A zero due to the

RCOMP-CCOMP network is set at the same value as

the maximum load RL2 pole.

The total transfer function is shown as F(s).G(s) at

the bottom of figure 20. For maximum load (plain

line), the load pole is exactly compensated by the

zero of the error amplifier, and the result is a

perfect first order decreasing slope until it reaches

the zero of the output capacitor ESR. The error

amplifier cut off then prevents definitely any further

spurious noise or resonance from disturbing the

regulation loop.

The point where the complete transfer function has

a unity gain is known as the regulation bandwidth

and has a double interest:

– The higher it is the faster will be the reaction to

an eventual load change, and the smaller will be

the output voltage change.

– The phase shift in the complete system at this

point has to be less than 135 ° to ensure a good

stability. Generally, a first order gives 90 ° of

phase shift, and 180 ° for a second order.

In figure 20, the unity gain is reached in a first order

slope, so the stability is ensured.

The dynamic load regulation is improved by

increasing the regulation bandwidth, but some

limitations have to be respected: As the transfer

function above the zero due the capacitor ESR is

not reliable (The ESR itself is not well specified,

and other parasitic effects may take place), the

bandwidth should always be lower than the

minimum of FC and ESR zero.

As the highest bandwidth is obtained with the

highest output power (Plain line with RL2 load in

figure 20), the above criteria will be checked for

this condition and allows to define the value of

RCOMP, as the error amplifier gain depends only

on this value for this frequency range. The

following formula can be derived:

With:

And:

The lowest load gives another condition for

stability: The frequency FBW1 must not encounter

the second order slope generated by the load pole

and the integrator part of the error amplifier. This

condition can be met by adjusting the CCOMP

value:

With:

The above formula gives a minimum value for

CCOMP. It can be then increased to provide a

natural soft start function as this capacitor is

charged by the error amplifier current capacity

ICOMPhi at start-up.

Figure 20: Complete Converter Transfer Function

G(S)

F(S)

F(S).G(S)

π R

L 1

OUT

⋅⋅

----------------------------------------

π R

L 2

OUT

⋅⋅

----------------------------------------

π ESR C

OUT

⋅⋅

⋅

------------------------------------------------

π R

COM P

CO M P

⋅⋅

⋅

----------------------------------------------------------------

FBW2

FBW1

3.2

MA X

OU T 2

--------------------

⋅

3.2

MAX

OUT1

--------------------

⋅

Gm R

COM P

⋅

COMP

OUT2

MAX

-----------------

BW 2 RL2 COUT

⋅⋅

------------------------------------------------

⋅

OUT2

OUT

--------------

MAX

--- L

LIM

⋅⋅

⋅

COMP

L1 COUT

⋅

6.3 Gm R

COMP

⋅⋅

---------------------------------------------

OUT1

MAX

-----------------

⋅

OUT1

OUT

--------------

VIPER53DIP Datasheet(PDF) 18 Page - STMicroelectronics

VIPER53DIP Datasheet(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL