VIPER0PLDTR datasheet(24/36 Pages) STMICROELECTRONICS

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General description

VIPer0P

24/36

DocID028423 Rev 2

VOUT could increases out of control and be maintained indefinitely at much higher value

than nominal one with risk for the output capacitor, the output diode and the IC itself. The

max duty cycle counter protection prevents this kind of failures.

4.14

VCC clamp protection

This protection can be invoked when the IC is supplied by auxiliary winding or diode from

the output voltage, when an output over-voltage produces an increase of VCC.

If VCC reaches the clamp level VCCclamp (30 V, min. referred to EAGND) the current injected

into the pin is monitored and if it exceeds the internal threshold Iclamp_max (30 mA, typ.) for

more than tclamp_max (5 ms, typ.), the PWM is disabled for tRESTART (1 sec, typ.) and then

activated again with soft-start phase. The protection is disabled during the soft-start time.

4.15

Thermal shutdown

If the junction temperature becomes higher than the internal threshold TSD (160 °C, typ.),

the PWM is disabled. After tRESTART time, a single switching cycle is performed, during

which the temperature sensor embedded in the Power MOSFET section is checked. If a

junction temperature above TSD is still measured, the PWM is maintained disabled for

tRESTART time, otherwise it resumes switching with soft-start phase.

During tRESTART VCC is maintained between VCSon and VCCon levels by the HV current source

periodical activation. Such a behavior is summarized in Figure 32: "Thermal shutdown

timing diagram".

Figure 32: Thermal shutdown timing diagram

time

CC on

CS on

DR AIN

DLIM

RES TAR T

J > TSD

J < TSD

PEA K

RES TAR T

GIPD270420151404MT

VIPER0PLDTR Datasheet(PDF) 24 Page - STMicroelectronics