L6706 datasheet(31/47 Pages) STMICROELECTRONICS

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L6706

Soft-start

Doc ID 15698 Rev 2

31/47

Soft-start

L6706 implements a soft-start to smoothly charge the output filter avoiding high in-rush

currents to be required to the input power supply. The device increases the reference from

zero up to the programmed value and the output voltage increases accordingly with closed

loop regulation.

The device implements soft-start only when all the power supplies are above their own turn-

on thresholds and the OUTEN pin is set free.

At the end of the digital soft-start, SS_END signal is set free.

Protections are active during soft-start: Under voltage is enabled when the reference voltage

reaches 0.6 V while over voltage is always enabled.

Figure 13.

Soft-start

Once L6706 receives all the correct supplies and enables, it initiates the soft-start phase

with a TD1 = 1.5 ms (typ) delay. After that, the reference ramps up to VBOOT = 1.081 V (1.100

V - 19 mV) in TD2 according to the SSOSC settings and waits for TD3 = 200 μsec (typ) during

which the device reads the VID lines. Output voltage will then ramps up to the programmed

value in TD4 with the same slope as before (See Figure 13).

SSOSC defines the frequency of an internal additional soft-start-oscillator used to step the

reference from zero up to the programmed value; this oscillator is independent from the

main oscillator whose frequency is programmed through the OSC pin.

The current flowing from SSOSC pin before the end of soft-start is used to program the

desiderated soft-start time (TSS).

After that the soft-start is finished the current flowing from SSOSC pin is used to program

the maximum LTB switching frequency (FLIMIT).

In the Figure 14 is shown the SSOSC connection in order to select both parameter (TSS and

FLIMIT) in independent way.

In particular, it allows to precisely programming the startup time up to VBOOT (TD2) since it is

a fixed voltage independent by the programmed VID. Total soft-start time dependence on

the programmed VID results (see Figure 15).

Note:

If during TD3 the programmed VID selects an output voltage lower than VBOOT, the output

voltage will ramp to the programmed voltage starting from VBOOT.

OUTEN

SS_END

VOUT

D3TD4

TSS

OVP

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