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L6718TR Datasheet(PDF) 34 Page - STMicroelectronics

Part # L6718TR
Description  SMBus interface for power management
PDF  71 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6718TR Datasheet(HTML) 34 Page - STMicroelectronics

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Device configuration
L6718
34/71
DocID023399 Rev 3
6.6.2
CONFIG0 in DDR mode (STCOMP=GND)
If the STCOM/DDR pin is short to GND, the device is set in DDR mode.
During startup, the CONFIG0/PSI0 pin works as CONFIG0 pinstrapping, and it is possible to
select the following (seeTable 9):
a)
Output voltage: VOUT can be selected to support DDR3 (1.5 V/1.35 V) and DDR4
(1.2 V). The only debug mode is for DDR3.
b)
SVID address: the serial VID address can be selected between 02h and 04h for
DDR3, while in DDR4 also the SVID address 06h or 08h can be selected. The
status of the SVID address can be used with the Address_Domain (settable by
CONFIG1 pinstrapping) to select also the SMBus address for the multi-phase rail
and the single-phase rail. See Table 14 for details.
c)
In DDR mode the debug configuration is not settable and SVID is set only in
operating mode (CLK to 25 MHz).
d)
SMBus: set SMBus OFF to disable SMBus function. As a consequence pins
CONFIG2/SDA and CONFIG3/SCL are used as pinstrapping CONFIG2 and
CONFIG3 (see Section 6.6.5 and Section 6.6.6). If SMBus is set ON, pins
CONFIG2/SDA and CONFIG3/SCL are set as serial data (SDA) and serial clock
(SCL) used for the SMBus communication (See Section 7.1).
e)
SWAP mode: set SWAP ON to enter SWAP mode. As a consequence all 3
embedded drivers run for the multi-phase rail (see Section 6.3).
27
20
ON
ON
Debug
01h
1.1 V
35 A
0 V
1.1 V
01h
1.1 V
150
15
ON
ON
Operating
01h
0 V
35 A
0 V
0 V
01h
0 V
1.
Suggested values, divider need to be connected between VCC5 pin and GND.
2.
The operating mode (SVID bus 25 MHz) is only with Vboot =0 V.
3.
The 0 V multi-phase rail Vboot is the only operating mode.
4.
If Jmode is OFF and MRO disabled, it is possible to select the single-phase rail maximum current and boot voltage.
5.
To select MRO see Section 6.3.1.
Table 8. CONFIG0/PSI0 pinstrapping in CPU MODE (continued)
Pinstrapping (1)
divider (KOhm)
SWAP
mode
SMBus
SVID (2)
status
Jmode ON (3)
Jmode OFF &
MRO disable (4)
MRO enable (5)
R up
R down
SVID
ADD
Multi
Vboot
SIMA
X
Multi
Vboot
Single
Vboot
SIMAX
/ ADD
Multi
Vboot



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