PM6675 datasheet(18/47 Pages) STMICROELECTRONICS

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Device description

PM6675

18/47

6.1.2

Output ripple compensation and loop stability

The loop is closed connecting the center tap of the output divider (internally, when the fixed

output voltage is chosen, or externally, using the VSEL pin in the adjustable output voltage

mode). The feedback node is the negative input of the error comparator, while the positive

input is internally connected to the reference voltage (Vr = 0.6V). When the feedback

voltage becomes lower than the reference voltage, the PWM comparator goes to high and

sets the control logic, turning on the high-side MOSFET. After the On-Time (calculated as

previously described), the system releases the high-side MOSFET and turns on the

synchronous rectifier.

The voltage drop along ground and supply PCB paths, used to connect the output capacitor

to the load, is a source of DC error. Furthermore the system regulates the output voltage

valley, not the average, as shown in Figure 9. Thus, the voltage ripple on the output

capacitor is an additional source of DC error. To compensate this error, an integrative

network is introduced in the control loop, by connecting the output voltage to the COMP pin

through a capacitor (CINT) as shown in Figure 7.

Figure 7.

Circuitry for output ripple compensation

The additional capacitor is used to reduce the voltage on the COMP pin when higher than

300mVpp and is unnecessary for most of applications. The trans conductance amplifier

(gm) generates a current, proportional to the DC error, used to charge the CINT capacitor.

The voltage across the CINT capacitor feeds the negative input of the PWM comparator,

forcing the loop to compensate the total static error. An internal voltage clamp forces the

COMP pin voltage range to ±150mV respect to VREF. This is useful to avoid or smooth

output voltage overshoot during a load transient. When the Pulse-Skip Mode is entered, the

clamping range is automatically reduced to 60mV in order to enhance the recovering

capability. If the ripple amplitude is larger than 150mV, an additional capacitor CFILT can be

connected between the COMP pin and ground to reduce ripple amplitude, otherwise the

integrator will operate out of its linearity range. This capacitor is unnecessary for most of

applications and can be omitted.

VREF

REF

COMP

VSNS

RFb1

Fb1

RFb2

Fb2

PWM

Comparator

CINT

INT

RINT

INT

CFILT

FILT

COUT

OUT

COMP PIN

VOLTAGE

OUTPUT

VOLTAGE

I=gm(V1-Vr)

V11

∆V

CINT

INT

ESR

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