PM6686 datasheet(45/50 Pages) STMICROELECTRONICS

45 / 50 page

PM6686

PCB design guidelines

Doc ID 15281 Rev 4

45/50

PCB design guidelines

The layout is very important in terms of efficiency, stability and noise of the system. It is

possible to refer to the PM6686 demonstration board for a complete layout example.

For good PC board layout follows these guidelines:

●

Place on the top side all the power components (inductors, input and output capacitors,

MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve

a layer to PGND plan. The PGND plan is the same for both the switching sections.

●

AC current paths layout is very critical (see Figure 58). The first priority is to minimize

their length. Trace the LS MOSFET connection to PGND plan as short as possible.

Place the synchronous diode D near the LS MOSFET. Connect the LS MOSFET drain

to the switching node with a short trace.

●

Place input capacitors near HS MOSFET drain. It is recommended to use the same

input voltage plan for both the switching sections, in order to put together all input

capacitors.

●

Place all the sensitive analog signals (feedbacks, voltage references, current sense

paths) on the bottom side of the board or in an inner layer. Isolate them from the power

top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in

one point (a multiple vias connection is preferable to a 0

Ω resistor connection) near the

PGND device pin. Place the device on the top or on the bottom size and connect the

exposed pad and the SGND pins to the SGND plan (see Figure 58).

●

As general rule, make the high-side and low-side drivers traces wide and short.

●

The high-side driver is powered by the bootstrap circuit. It’s very important to place

capacitor CBOOT as near as possible to the BOOT pin (for example on the layer

opposite to the device). Route HGATE and PHASE traces as near as possible in order

to minimize the area between them.

●

The low-side gate driver is powered by PVCC pin. Placing PGND and LGATE pins near

the low-side MOSFETs reduces the length of the traces and the crosstalk noise

between the two sections.

●

The linear regulator outputs are referred to SGND as long as the reference voltages

VREF2 and VREF3. Place their output filtering capacitors as near as possible to the

device.

●

Place input filtering capacitors near PVCC, VCC and VIN pins.

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