ST7DALIF2 datasheet(78/171 Pages) STMICROELECTRONICS

78 / 171 page

12-bit autoreload timer 2 (AT2)

ST7DALIF2

78/171

Bits 4:3 = CK[1:0] Counter Clock Selection.

These bits are set and cleared by software and cleared by hardware after a reset. They

select the clock frequency of the counter.

Bit 2 = OVF Overflow Flag.

This bit is set by hardware and cleared by software by reading the TCSR register. It

indicates the transition of the counter from FFFh to ATR value.

0: No counter overflow occurred

1: Counter overflow occurred

Bit 1 = OVFIE Overflow Interrupt Enable.

This bit is read/write by software and cleared by hardware after a reset.

0: OVF interrupt disabled.

1: OVF interrupt enabled.

Bit 0 = CMPIE Compare Interrupt Enable.

This bit is read/write by software and cleared by hardware after a reset. It can be used to

mask the interrupt generated when the CMPF bit is set.

0: CMPF interrupt disabled.

1: CMPF interrupt enabled.

14.6.2

Counter register high (CNTRH)

Read only

Reset Value: 0000 0000 (000h)

14.6.3

Counter register low (CNTRL)

Read only

Reset Value: 0000 0000 (000h)

Bits 15:12 = Reserved.

Bits 11:0 = CNTR[11:0] Counter Value.

This 12-bit register is read by software and cleared by hardware after a reset. The counter is

incremented continuously as soon as a counter clock is selected. To obtain the 12-bit value,

Table 38.

Counter clock frequency

Counter clock selection

CK1

CK0

OFF

fLTIMER (1 ms timebase @ 8 MHz)

(1)

PWM mode and Output Compare modes are not available at this frequency.

fCPU

32 MHz (2)

ATICR counter may return inaccurate results when read. It is therefore not recommended to use Input

Capture mode at this frequency.

CNTR

CNTR9

CNTR8

CNTR7

CNTR6

CNTR5

CNTR4

CNTR3

CNTR2

CNTR1

CNTR0

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