ST7MC1K2 datasheet(88/371 Pages) STMICROELECTRONICS

88 / 371 page

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Note:

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is

cleared).

Watchdog reset on HALT option

If the watchdog is activated and the watchdog reset on halt option is selected, then the HALT

instruction generates a reset.

10.1.4

Using Halt mode with the watchdog

If Halt mode with watchdog is enabled by option byte (no watchdog reset on HALT

instruction), it is recommended before executing the HALT instruction to refresh the WDG

counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

10.1.5

How to program the watchdog timeout

Figure 31 shows the linear relationship between the 6-bit value to be loaded in the watchdog

counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a

quick calculation without taking the timing variations into account. If more precision is

needed, use the formulae in Figure 32.

Caution:

When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 31.

Approximate timeout duration

Watchdog timeout (ms) @ 8 MHz fOSC2

128

1.5

114

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ST7MC1K2 Datasheet(PDF) 88 Page - STMicroelectronics