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ST72561K9-Auto Datasheet(PDF) 44 Page - STMicroelectronics |
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ST72561K9-Auto Datasheet(HTML) 44 Page - STMicroelectronics |
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44 / 324 page  Supply, reset and clock management ST72561-Auto 44/324 Doc ID 12370 Rev 8 The reset vector fetch phase duration is two clock cycles. Figure 12. RESET sequence phases 5.5.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Chapter 20: Electrical characteristics for more details. A reset signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 14). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. Figure 13. Reset block diagram The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 5.5.3 External power-on reset If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 5.5.4 Internal low voltage detector (LVD) reset Two different reset sequences caused by the internal LVD circuitry can be distinguished: ● Power-on reset ● Voltage drop reset RESET Active Phase INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR RESET RON VDD WATCHDOG RESET LVD RESET INTERNAL RESET PULSE GENERATOR Filter |
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