ST72561J6-Auto datasheet(43/324 Pages) STMICROELECTRONICS

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ST72561-Auto

Supply, reset and clock management

Doc ID 12370 Rev 8

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output distortion and start-up stabilization time. The loading capacitance values must be

adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the

oscillator start-up phase.

5.5

Reset sequence manager (RSM)

5.5.1

Introduction

The reset sequence manager includes three RESET sources as shown in Figure 13:

●

External RESET source pulse

●

Internal LVD reset (Low Voltage Detection)

●

Internal watchdog reset

These sources act on the RESET pin and it is always kept low during the delay phase.

The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory

map.

The basic RESET sequence consists of three phases as shown in Figure 12:

●

Active phase depending on the reset source

●

256 or 4096 CPU clock cycle delay (selected by option byte)

●

RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that

recovery has taken place from the Reset state. The shorter or longer clock cycle delay

should be selected by option byte to correspond to the stabilization time of the external

oscillator used in the application.

Table 8.

ST7 clock sources

Hardware configuration

OSC1

OSC2

EXTERNAL

ST7

SOURCE

OSC1

OSC2

LOAD

CAPACITORS

ST7

CL2

CL1

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