STM8TL53X4 datasheet(46/84 Pages) STMICROELECTRONICS

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Electrical parameters

STM8TL52x4 STM8TL53x4

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DocID022344 Rev 7

9.3.2

Power supply

Figure 10. Power supply scheme

1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These

capacitors must be placed as close as possible to, or below, the appropriate pins to ensure the correct

functionality of the device.

2. The 1µF capacitor must be connected to the VDD pin.

The 1µF ceramic capacitor connected to PXS_VREG must be low ESR (

9.3.3

Power-up / power-down operating conditions

ESR 1





Table 17. Operating conditions at power-up / power-down

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

tVDD

VDD rise time rate

1300

µs/V

tTEMP

Reset release delay

VDD rising

VPOR

Power on reset threshold

1.44(2)

-1.65(1)

1. Tested in production.

VPDR

Power down reset threshold

1.30(2)

-1.60(2)

2. Data based on characterization results, not tested in production.

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