TP3054J datasheet(2/16 Pages) NSC

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Block Diagram

FIGURE 1

TLH5510 – 2

Pin Description

Symbol

Function

VBB

Negative power supply pin

VBB eb5V g5%

GNDA

Analog ground All signals are referenced

to this pin

VFRO

Analog output of the receive power ampli-

fier

VCC

Positive power supply pin

VCC ea5V g5%

FSR

Receive frame sync pulse which enables

BCLKR to shift PCM data into DR FSR is

an 8 kHz pulse train See

Figures 2 and 3

for timing details

Receive data input PCM data is shifted

into DR following the FSR leading edge

BCLKR CLKSEL The bit clock which shifts data into DR af-

ter the FSR leading edge May vary from

64 kHz to 2048 MHz Alternatively may

be a logic input which selects either

1536 MHz1544 MHz or 2048 MHz for

master clock in synchronous mode and

BCLKX is used for both transmit and re-

ceive directions (see Table I)

MCLKR PDN

Receive

master

clock

Must

1536 MHz 1544 MHz or 2048 MHz

May be asynchronous with MCLKX but

Symbol

Function

should be synchronous with MCLKX for best per-

formance When MCLKR is connected continu-

ously low MCLKX is selected for all internal tim-

ing When MCLKR is connected continuously

high the device is powered down

MCLKX

Transmit master clock Must be 1536 MHz

1544 MHz or 2048 MHz May be asynchronous

with MCLKR Best performance is realized from

synchronous operation

FSX

Transmit frame sync pulse input which enables

BCLKX to shift out the PCM data on DX FSX is

an 8 kHz pulse train see

Figures 2 and 3 for

timing details

BCLKX

The bit clock which shifts out the PCM data on

DX May vary from 64 kHz to 2048 MHz but

must be synchronous with MCLKX

The TRI-STATE

PCM data output which is en-

abled by FSX

TSX

Open drain output which pulses low during the

encoder time slot

GSX

Analog output of the transmit input amplifier

Used to externally set gain

VFXIb

Inverting input of the transmit input amplifier

VFXIa

Non-inverting input of the transmit input amplifi-

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