STM32F769II datasheet(25/255 Pages) STMICROELECTRONICS

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DocID029041 Rev 4

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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

Functional overview

2.10

LCD-TFT controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)

and delivers all signals to interface directly to a broad range of LCD and TFT panels up to

XGA (1024x768) resolution with the following features:

•

2 display layers with dedicated FIFO (64x32-bit)

•

Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer

•

Up to 8 input color formats selectable per layer

•

Flexible blending between two layers using alpha value (per pixel or constant)

•

Flexible programmable parameters for each layer

•

Color keying (transparency color)

•

Up to 4 programmable interrupt events

2.11

Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit

blitting, row data copy and pixel format conversion. It supports the following functions:

•

Rectangle filling with a fixed color

•

Rectangle copy

•

Rectangle copy with pixel format conversion

•

Rectangle composition with blending and pixel format conversion

Various image format codings are supported, from indirect 4bpp color mode up to 32bpp

direct color. It embeds dedicated memory to store color lookup tables.

An interrupt can be generated when an operation is complete or at a programmed

watermark.

All the operations are fully automatized and are running independently from the CPU or the

DMAs.

2.12

Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-

M7 with FPU core.

•

Closely coupled NVIC gives low-latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Allows early processing of interrupts

•

Processing of late arriving, higher-priority interrupts

•

Support tail chaining

•

Processor state automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

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