TP3070 datasheet(4/26 Pages) NSC

4 / 26 page

Functional Description (Continued)

POWER-DOWN STATE

Following a period of activity in the powered-up state the

power-down state may be re-entered by writing any of the

control instructions into the serial control port with the “P” bit

set to “1” as indicated in

Table 1. It is recommended that the

chip be powered down before writing any additional instruc-

tions. In the power-down state, all non-essential circuitry is

de-activated and the D

X0 (and DX1) outputs are in the high

impedance TRI-STATE condition.

The coefficients stored in the Hybrid Balance circuit and the

Gain Control registers, the data in the LDR and ILR, and all

control bits remain unchanged in the power-down state un-

less changed by writing new data via the serial control port,

which remains active. The outputs of the Interface Latches

also remain active, maintaining the ability to monitor and

control the SLIC.

TRANSMIT FILTER AND ENCODER

The Transmit section input, VF

XI, is a high impedance sum-

ming input which is used as the differencing point for the in-

ternal hybrid balance cancellation signal. No external com-

ponents are necessary to set the gain. Following this circuit

is a programmable gain/attenuation amplifier which is con-

trolled by the contents of the Transmit Gain Register (see

Programmable Functions section). An active pre-filter then

precedes the 3rd order high-pass and 5th order low-pass

switched capacitor filters. The A/D converter has a com-

pressing characteristic according to the standard CCITT A or

µ255 coding laws, which must be selected by a control in-

struction during initialization (see

Table 1 and Table 2). A pre-

cision on-chip voltage reference ensures accurate and highly

stable transmission levels. Any offset voltage arising in the

gain-set amplifier, the filters or the comparator is canceled by

an internal auto-zero circuit.

Each encode cycle begins immediately following the as-

signed Transmit time-slot. The total signal delay referenced

to the start of the time-slot is approximately 165 µs (due to

the Transmit Filter) plus 125 µs (due to encoding delay),

which totals 290 µs. Data is shifted out on D

X0orDX1 during

the selected time slot on eight rising edges of BCLK.

DECODER AND RECEIVE FILTER

PCM data is shifted into the Decoder’s Receive PCM Regis-

ter via the D

R0orDR1 pin during the selected time-slot on

the 8 falling edges of BCLK. The Decoder consists of an ex-

panding DAC with either A or µ255 law decoding character-

istic, which is selected by the same control instruction used

to select the Encode law during initialization. Following the

Decoder is a 5th order low-pass switched capacitor filter with

integral Sin x/x correction for the 8 kHz sample and hold. A

programmable gain amplifier, which must be set by writing to

the Receive Gain Register, is included, and finally a Power

Amplifier capable of driving a 300

Ω load to ±3.5V, a 600Ω

load to ±3.8V or a 15 k

Ω load to ±4.0V at peak overload.

A decode cycle begins immediately after the assigned re-

ceive time-slot, and 10 µs later the Decoder DAC output is

updated. The total signal delay is 10 µs plus 120 µs (filter de-

lay) plus 62.5 µs (1⁄2 frame) which gives approximately 190

µs.

PCM INTERFACE

The FS

X and FSR frame sync inputs determine the begin-

ning of the 8-bit transmit and receive time-slots respectively.

They may have any duration from a single cycle of BCLK

HIGH to one MCLK period LOW. Two different relationships

may be established between the frame sync inputs and the

actual time-slots on the PCM busses by setting bit 3 in the

Control Register (see

Table 2). Non-delayed data mode is

similar to long-frame timing on the TP3050/60 series of de-

vices (COMBO); time-slots begin nominally coincident with

the rising edge of the appropriate FS input. The alternative is

to use Delayed Data mode, which is similar to short-frame

sync timing on COMBO, in which each FS input must be high

at least a half-cycle of BCLK earlier than the time-slot. The

Time-Slot Assignment circuit on the device can only be used

with Delayed Data timing.

When using Time-Slot Assignment, the beginning of the first

time-slot in a frame is identified by the appropriate FS input.

The actual transmit and receive time-slots are then deter-

mined by the internal Time-Slot Assignment counters.

Transmit and Receive frames and time-slots may be skewed

from each other by any number of BCLK cycles. During each

assigned Transmit time-slot, the selected D

X0/1 output shifts

data out from the PCM register on the rising edges of BCLK.

X0 (or TSX1 as appropriate) also pulls low for the first 7

⁄2

bit times of the time-slot to control the TRI-STATE Enable of

a backplane line-driver. Serial PCM data is shifted into the

selected D

R0/1 input during each assigned Receive time-slot

on the falling edges of BCLK. D

X0orDX1 and DR0orDR1

are selectable on the TP3070 only, see Section 6.

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