AD6311

1/8- to 1/16 Duty VFD Controller/Driver

Anachip Corp.

www.anachip.com.tw

Rev. A5 Dec 29, 2003

8/11

5.0 SW Data

The SW data is read by a read command, starting from the least significant bit. Bits 5 through 8 of the

SW data are 0.

0

0

0

0 b3 b2 b1 b0

MSB

LSB

SW1

SW2

SW3

SW4

Timing Diagram

(1) Serial Communication Format

Reception (command/write data)

If data continues

STB

b7

b6

b2

b1

b0

8

7

3

2

1

CLK

Transmission (read data)

6

5

4

3

2

1

8

7

6

5

4

3

2

1

b7

b6

b5

b4

b3

b2

b1

b0

b0

b1

b2

b3

b4

b5

STB

CLK

Data reading starts.

Data reading command is set.

(Note)

this pin (1kΩ to 10 kΩ).

falling of the first clock that has read the data.