AD6312 datasheet(2/13 Pages) ETC

2 / 13 page

AD6312

1/4- to 1/11 Duty VFD Controller/Driver

Anachip Corp.

www.anachip.com.tw

Rev. A4 Dec 29, 2003

2/13

Pin Descriptions

Symbol

Name

No.

Description

DIN

Data input

Input serial data at rising edge of shift clock,

starting from the low order bit.

DOUT

Data output

Output serial data at the falling edge of the shift

clock, starting from low order bit. This is N-ch

open-drain output pin.

STB

Strobe

Initializes serial interface at the rising or falling

edge of the AD6312. It then waits for reception of

a command. Data input after STB falling is

processed as a command. While command data

is processed, current processing is stopped, and

the serial interface is initialized. While STB is

high, CLK is ignored.

CLK

Clock input

Reads serial data at the rising edge, and outputs

data at the falling edge.

OSC

Oscillator pin

Connect resistor in between this pin and Vss to

set up the oscillation frequency.

Seg7 to Seg11

High-voltage output (Segment)

21 to 25

Segment output pins

Seg1/KS1 to

Seg6/KS6

High-voltage output

15 to 20

Multi-function pins, Segment output pins (Dual

function as key scan source)

Grid1 to Grid6

High-voltage output (Grid)

32 to 37

Grid output pins

Seg12/Grid11 to

Seg16/Grid7

High-voltage output (Segment/grid)

26,

28 to 31

These pins are selectable for segment or grid

driving.

LED1 to LED4

LED output

39to 42

CMOS output

KEY1 to KEY4

Key data input

10 to 13

Data input to these pins is latched at the end of

the display cycle.

VDD

Logic power

14, 38

Logic power supply

VSS

Logic ground

7, 43

Connect this pin to system GND.

VEE

Pull-down level

Driver power supply

SW1 to SW4

Switch input

1 to 4

These pins constitute a 4-bit general-purpose

input port.

Ordering Information

AD6312 X X X

Packing

Blank : Tray

Q: QFP-44L

Package

Lead

Blank: Normal

F: Lead Free

L: LQFP-44L

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