REV. A

–10–

AD9845B

PIXEL GAIN AMPLIFIER (PxGA) TIMING

FRAME N

LINE 0

LINE 1

LINE 2

LINE M

0101...

2323...

0101...

LINE M–1

LINE 0

LINE 1

LINE 2

LINE M

0101...

2323...

0101...

LINE M–1

0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3

FRAME N+1

VD

HD

Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence

SHP

HD

3ns MIN

3ns MIN

PxGA GAIN

GAIN0

GAIN1

GAIN0

GAIN3

GAIN2

GAINX

GAINX

VD

NOTES

1. MINIMUM PULSEWIDTH FOR HD AND VD IS FIVE PIXEL CYCLES.

2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SETUP TIME IS 3 ns.

3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.

4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.

5 PIXEL MIN

Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing

0101...

2323...

0101...

0101...

2323...

0101...

HD

LINE 0

LINE 1

LINE 2

LINE M

LINE M–1

LINE 0

LINE 1

LINE 2

LINE M

LINE M–1

EVEN FIELD

ODD FIELD

0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3

VD

Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence

SHP

HD

PxGA

GAIN

GAIN0

GAIN1

GAIN0

GAIN3

GAIN2

GAINX

GAINX

3ns MIN

3ns MIN

5 PIXEL MIN

VD

NOTES

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.

2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101.

3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.

Figure 11. PxGA Mode 2 (Interlace) Detailed Timing