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TPS72011DRVT Datasheet(PDF) 17 Page - Texas Instruments |
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TPS72011DRVT Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 33 page ![]() OUT NC EN IN GND BIAS 1 2 3 6 5 4 COUT CIN CBIAS To Bias Supply To Input Supply To Load To Enable Signal Ground Plane Ground Plane TPS720 www.ti.com SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015 9 Power Supply Recommendations The input supply and bias supply for the LDO must be within its recommended operating conditions and provide adequate headroom for the device to have a regulated output. The minimum capacitor requirements must be met, and if the input supply is noisy, then additional input capacitors with low ESR can help improve transient performance. 10 Layout 10.1 Layout Guidelines To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the board with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should be connected directly to the GND pin of the device. High equivalent series resistance (ESR) capacitors may degrade PSRR. The BIAS pin draws very little current and can be routed as a signal (make sure to shield it from high-frequency coupling). 10.2 Layout Example Figure 33. Recommended Layout 10.3 Thermal Considerations Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: TPS720 |
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