In the same manner the time-slot number should be written

into the appropriate TSR registers for receive data at the BO

and DO pins TSRB1 is the time-slot assignment for the

receive B1 channel TSRB2 is the time-slot assignment reg-

ister for the receive B2 channel and TSRD is the sub-slot

assignment register for the receive D channel

Whenever any receive time-slot is active at BO the TSB

output is also pulled low

REGISTERS TSXB1 TSXB2 TSRB1 TSRB2

The data format for all B channel time-slot assignment reg-

isters is shown in Table IV

Bit 7 Transparency Control EB

This bit enables or disables data transparency between the

digital interface and the line interface for the selected chan-

nel

When the transmit direction (towards the line) is disabled

there will be all ‘‘ONE’s’’ (scrambled) as data for this chan-

nel at the Lo pin If the receive direction (from the line) is

disabled BO will stay high impedance for the programmed

time slot while if it is enabled data out on BO in the as-

signed time slot is the data from Li

Bits 5 – 0 TS5 – TS0

These bits define the binary number of the time-slot select-

ed Time-slots are numbered from 0 – 63 The frame sync

signal is used as marker pulses for the beginning of time

slot 0

TABLE IV Byte 2 of Register TSXB1 TSXB2 TSRB1 or

TSRB2 for B Channel Time-Slot Assignment

Bit Number and Name

Function

7

6

543210

EB

X

TS5

TS4

TS3

TS2

TS1

TS0

0

X

XXXXXX

Disable B1

andor B2

1

X

Assign One Binary Coded Time-Slot

Enable B1 andor

from 0–63

B2

Note

If two B channels are erroneously assigned to the same time-slot

data out on Bo is not valid while data out on Lo is valid

REGISTERS TXD TRD

The data format for all D channel time-slot assignment reg-

isters is as follows

Data transparency between the digital interface and the line

interface for the D channels can be controlled via the Chan-

nel Control Register see Table III

Bits 7 – 0 TS7 – TS0

These bits define the binary number of the sub-slot select-

ed Sub-slots are numbered from 0 – 255 The frame sync

signal is used as marker pulses for the beginning of Sub-slot

0

TABLE V Byte 2 of Register TSXD or TSRD for D

Channel Time-Slot Assignment

Bit Number and Name

76543210

SS

SS

SS

SS

SS

SS

SS

SS

76543210

Assign One Binary Coded Sub-Slot from 0–255 for D Channel

TLH11924 – 6

FIGURE 4 QDASL Digital Interface Timing

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