DG2302DL datasheet(2/4 Pages) VISHAY

2 / 4 page

DG2302

Vishay Siliconix

New Product

www.vishay.com

Document Number: 72072

s-03421—Rev. A, 03-Mar-03

ABSOLUTE MAXIMUM RATINGS

Reference to GND

V+

-0.3 to +6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OE, A, Ba

-0.3 to (V+ + 0.3 V)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous Current (Any terminal)

"50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak Current

"200 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(Pulsed at 1 ms, 10% duty cycle)

Storage Temperature (D Suffix)

-65 to 150

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Dissipation (Packages)b

5-Pin SC70c

250 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Notes:

Signals on A, or B or OE exceeding V+ will be clamped by internal

diodes. Limit forward diode current to maximum current ratings.

All leads welded or soldered to PC Board.

Derate 3.1 mW/

_C above 70_C

SPECIFICATIONS (V+ = 5.0 V)

Test Conditions

Otherwise Unless Specified

Limits

- 40 to 85

Parameter

Symbol

V+ = 5 V,

"10%, VIN = 0.8 or 2.0 Ve

Tempa

Minb

Typc

Maxb

Unit

DC Characteristics

V+ = 4.5 V, VA = 0 V, IB = 64 mA

Full

On-Resistance

rON

V+ = 4.5 V, VA = 0 V, IB = 30 mA

Full

V+ = 4.5 V, VA = 2.4 V, IB = 15 mA

Full

Switch Off Leakage Current

I(off)

V+ = 5.5 V, VA = 1 V/4.5 V, VB = 4.5 V/1 V

Full

-10

Switchl-On Leakage Current

I(on)

V+ = 5.5 V, VA = VB = 1 V/4.5 V

Full

-10

Input High Voltage

VIH

Full

2.0

Input Low Voltage

VIL

Full

0.8

Input Current

IIL or IIH

VOE = 0 or V+

Full

-1

Dynamic Characteristics

Prop Delay Bus to Busf

tPHL

VLD = Open (Figure 1 and 2)

Full

Prop Delay Bus-to-Busf

tPLH

VLD = Open (Figure 1 and 2)

Full

Output Enable Timed

tPZL

VLD = 7 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)

Full

5.0

Output Enable Timed

tPZH

VLD = Open, V+ = 4.5 V to 5.5 V (Figure 1 and 2)

Full

5.0

Output Disable Timed

tPLZ

VLD = 7 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)

Full

3.9

Output Disable Timed

tPHZ

VLD = Open, V+ = 4.5 V to 5.5 V (Figure 1 and 2)

Full

1.0

Input Capacitance

Cin

Room

3.5

Channel-Off Capacitanced

C(off)

VOE = 0 or V+ f = 1 MHz

Room

Channel-On Capacitanced

CON

VOE = 0 or V+, f = 1 MHz

Room

Power Supply

Power Supply Range

V+

4.0

5.5

Power Supply Current

I+

VOE = 0

0.9

1.5

Power Supply Current

I+

VOE = V+

1.0

Notes:

Room = 25

°C, Full = as determined by the operating suffix.

The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

Typical values are for design aid only, not guaranteed nor subject to production testing.

Guarantee by design, nor subjected to production test.

VIN = input voltage to perform proper function.

Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the on-resistance and

the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch.

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