3.3V

TLV803S

DSP/FPGA/ASIC

GND

GND

RESET

RESET

V

DD

3.3-VLDO

GND

OUT

IN

5V

V

DD

GND

V

DD

RESET

RST

TLV803Z

Microprocessor

10kW

0.1 mF

2.5V

5.0V

TLV803, TLV853, TLV863

SBVS157C – APRIL 2011 – REVISED SEPTEMBER 2015

www.ti.com

Application Information (continued)

Figure 12. Output Voltage Level Shifting

9.2 Typical Application

Figure 13 shows TLV803S being used to monitor the supply rail for a DSP, FPGA, or ASIC.

Figure 13. Typical Application

9.2.1 Design Requirements

This design calls for a 3.3-V rail to be monitored. The design resets if the supply rail falls below 2.93 V. The

output must satisfy 3.3-V CMOS logic.

9.2.2 Detailed Design Procedure

Select the TLV803S to satisfy the voltage threshold requirement.

Place a pullup resistor on RESET to VDD in order to satisfy the output logic requirement.

10

Submit Documentation Feedback

Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: TLV803 TLV853 TLV863