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M54HC75K1 Datasheet(PDF) 1 Page - STMicroelectronics |
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M54HC75K1 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 10 page ![]() 1/10 June 2004 s HIGH SPEED: tPD = 11ns (TYP.) at VCC =6V s LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH =VNIL = 28% VCC (MIN.) s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL =4mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 75 s SPACE GRADE-1: ESA SCC QUALIFIED s 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST s NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION s DEVICE FULLY COMPLIANT WITH SCC-9203-065 DESCRIPTION The M54HC75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. It contains two groups of 2 bit latches controlled by an enable input (G1 •2or G3•4). These two latch groups can be used in different circuits. Each latch has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The data applied to the data input is transferred to the Qand Q outputs when the enable input is taken high and the outputs will follow the data input as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input is retained at the outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M54HC75 RAD HARD 4 BIT D TYPE LATCH PIN CONNECTION ORDER CODES PACKAGE FM EM DILC M54HC75D M54HC75D1 FPC M54HC75K M54HC75K1 DILC-16 FPC-16 Rev. 1 |
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