TABLE I

(Continued)

Reg

RW

Description

(in HEX)

46

Bit 7 is

IDE CHANNEL 1 READ

AHEAD COUNTER HIGH BYTE

RW

It provides values for loading bit8 – bit9 of read

ahead counter

others

bit0

bit8 of the readahead counter

are WO

bit1

bit9 of the readahead counter

bit7

readahead function control

1 enable

0 disable (default)

47

IDE CHANNEL 1 FUNCTION REGISTER

bit3

channel 1 IO decode enable bit

1 enable (default)

0 disable

bit2

IORDY1 function control

1 enable

0 disable (default)

bit1

CH1INT status (read only)

1 interrupt pending

0 no interrupt pending

bit0

CH1INT request to be masked or not

1 be masked

0 not be masked (default)

48

PCI CONTROL REGISTER

bit3

host posted write cycle timing select

1 min 1 wait state (default)

0 min 0 wait state (Note 2)

bit2

active HDDRST

output active control

1 activate HDDRST (default)

0 No action

bit1

DEVSEL

timing select

1 medium (default)

0 fast

bit0

Header for IDE support on PCI is present or not

1 present

0 absent Default

Values is determined by the ‘‘Header Pin’’

49 – 4F

Not used

Note 1

Total cycle time is calculated by adding setup time hold time and active time plus 1 clk

Note 2

When 0 wait state is used then DEVSEL

timing select bit should be set to 0 (fast)

Note 3

If register 40 is 00 then IORDY0 should be disabled

If register 44 is 00 then IORDY1 should be disabled

10