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TC90A49F Datasheet(PDF) 3 Page - Toshiba Semiconductor |
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TC90A49F Datasheet(HTML) 3 Page - Toshiba Semiconductor |
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3 / 17 page ![]() TC90A49P/F 2001-03-06 3/17 PIN DESCRIPTION no. before / indicates DIP package pin no. no. after / indicates SOP package pin no. PIN No. PIN NAME FUNCTION I / O INTERFACE 1 VDD2 ADC and DAC analog power supply. − − 2 BIAS ADC bias voltage. Stabilize by attaching a 0.01µF capacitor. − 3 VRT ADC input range D upper limit voltage. Stabilize by attaching a 0.01µF capacitor. − 4 / 5 AIN ADC input. Inputs 1.0 Vp-p video signal. Sync tip clamp is performed. I 5 / 6 VRB ADC input range D lower limit voltage. Stabilize by attaching a 0.01µF capacitor. − 6 / 7 VDD3 ADC and DAC logic power supply. − − 7 / 8 VSS2 Logic and internal DRAM GND (digital). − − 8 / 10 VDD4 Internal DRAM power supply. − − 9 / 11 SDA I 2 C BUS SDA I / O 10 / 12 SCL I 2 C BUS SCL I |
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