TP112 datasheet(4/8 Pages) ETC

4 / 8 page

TP112

TP112-DS-P02

Jan 5, 2000

PIN Description (continued)

PIN NO.

LABEL

TYPE

DESCRIPTION

Modes

MDC

Management Data Clock

MII management data clock input, maximum clock rate is

2.5MHz

MDIO

I/O

Management Data I/O

MII management data input/output

TMODE

Test Mode

Active high. Set TP112 into test mode, and low for normal

operation. There’s an internal pull low resistor so default is

normal operation

HALFONLY

I/IPL

Half Duplex Mode Only

1: half duplex

0: full duplex

FORCEON

I/IPL

Force Mode Enable

1: force mode enable

0: auto negotiation mode enable

LEDs

FDXLED*

Full Duplex LED

Before link OK, this pin is tri-stated. After link OK this pin

indicate current duplex operation for TP112. High for half

duplex and low for full duplex

LRLED*

FXLRLED*

Link/Receive LED

Active low. Indicates the link status of the port, driven low

when link to the port is good. Output for 20mS clock while the

TP112 is receiving data from external media

TXLED*

FXTLED*

Transmit LED

Active low. Indicates that data is being transmitting

Reset & Clock

RESET*

Reset

Active low. Reset TP112, remain low at least 1us.

OSCI/X1

Oscillator input or crystal input

(25MHz±50ppm).

Crystal output. Leave it unconnected (i.e., as a NC pin) when

oscillator is used.

Current Reference

BGRES

Band Gap Resistor

A 6.2KOhm 1% resistor that supply 200uA reference current

for receive

BGGND

Band Gap Resistor Ground

Band gap resistor ground reference input

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