VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8117

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Page 8

© VITESSE SEMICONDUCTOR CORPORATION

G52221-0, Rev 4.1

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

1/8/00

Clock Recovery

The fully monolithic Clock Recovery Unit (CRU) consists of a Phase Detector, a Frequency Detector, a

Loop Filter and a Voltage Controlled Oscillator (VCO). The phase detector compares the phase information of

the incoming data with the recovered clock. The frequency detector compares the frequency component of the

data input with the recovered clock to provide the pull in energy during lock acquisition. The Loop Filter inte-

grates the phase information from the phase and frequency detectors and provides the control voltage to the

VCO.

Jitter Tolerance

Jitter Tolerance is the ability of the Clock Recovery Unit to track timing variation in the received data

stream. The Bellcore and ITU specifications allow the received optical data to contain jitter. The amount that

must be tolerated is a function of the frequency of the jitter. At high frequencies the specifications do not require

the CRU to tolerate large amounts, whereas at low frequencies many unit intervals (bit times) of jitter have to be

tolerated. The CRU is designed to tolerate this jitter with margin over the specification limits, see Figure 7. The

CRU obtains and maintains lock based on the data transition information. When there is no transition on the

data stream, the recovered clock frequency can drift. The VSC8117 can maintain lock over 100 bits of no

switching on the data stream.

Figure 7: Jitter Tolerance

10

30

300

15

1.5

0.15

2.5M

150

60

6

0.5

Bellcore Requirement

VSC8117 Guaranteed

Jitter Tolerance