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LT1766/LT1766-5

1766fa

Thermal resistance for the LT1766 packages is influenced

by the presence of internal or backside planes.

SSOP (GN16) Package: With a full plane under the GN16

package, thermal resistance will be about 85

°C/W.

TSSOP (Exposed Pad) Package: With a full plane under the

TSSOP package, thermal resistance will be about 45

°C/W.

To calculate die temperature, use the proper thermal

resistance number for the desired package and add in

worst-case ambient temperature:

TJ = TA + (θJA • PTOT)

When estimating ambient, remember the nearby catch

diode and inductor will also be dissipating power:

DIODE

OUT

LOAD

( )(

–

)(

)

VF = Forward voltage of diode (assume 0.63V at 1A)

DIODE ==

)(

– )( )

063 40 5 1

055

PINDUCTOR = (ILOAD)2 (RL)

RL = Inductor DC resistance (assume 0.1Ω)

PINDUCTOR (1)2 (0.1) = 0.1W

Only a portion of the temperature rise in the external

inductor and diode is coupled to the junction of the LT1766.

Based on empirical measurements the thermal effect on

LT1766 junction temperature due to power dissipation in

the external inductor and catch diode can be calculated as:

∆TJ(LT1766) ≈ (PDIODE + PINDUCTOR)(10°C/W)

Using the example calculations for LT1766 dissipation,

the LT1766 die temperature will be estimated as:

TJ = TA + (θJA • PTOT) + [10 • (PDIODE + PINDUCTOR)]

With the GN16 package (

θJA = 85°C/W), at an ambient

temperature of 60

°C:

TJ = 60 + (85 • 0.53) + (10 • 0.65) = 112°C

With the TSSOP package (

θJA = 45°C/W), at an ambient

temperature of 60

°C:

TJ = 60 + (45 • 0.53) + (10 • 0.65) = 90°C

APPLICATIO S I FOR ATIO

Die temperature can peak for certain combinations of VIN,

VOUT and load current. While higher VIN gives greater

switch AC losses, quiescent and catch diode losses, a

lower VIN may generate greater losses due to switch DC

losses. In general, the maximum and minimum VIN levels

should be checked with maximum typical load current for

calculation of the LT1766 die temperature. If a more

accurate die temperature is required, a measurement of

the SYNC pin resistance (to GND) can be used. The SYNC

pin resistance can be measured by forcing a voltage no

greater than 0.5V at the pin and monitoring the pin current

over temperature in an oven. This should be done with

minimal device power (low VIN and no switching

(VC = 0V)) in order to calibrate SYNC pin resistance with

ambient (oven) temperature.

Note: Some of the internal power dissipation in the IC, due

to BOOST pin voltage, can be transferred outside of the IC

to reduce junction temperature, by increasing the voltage

drop in the path of the boost diode D2 (see Figure 9). This

reduction of junction temperature inside the IC will allow

higher ambient temperature operation for a given set of

conditions. BOOST pin circuitry dissipates power given

by:

DISS BOOST

OUT

()

•(

) •

Typically VC2 (the boost voltage across the capacitor C2)

equals Vout. This is because diodes D1 and D2 can be

considered almost equal, where:

VC2 = VOUT – VFD2 – (–VFD1) = VOUT

Hence the equation used for boost circuitry power dissipa-

tion given in the previous Thermal Calculations section is

stated as:

DISS BOOST

OUT

()

•(

)•

Here it can be seen that boost power dissipation increases

as the square of VOUT. It is possible, however, to reduce

VC2 below VOUT to save power dissipation by increasing

the voltage drop in the path of D2. Care should be taken

that VC2 does not fall below the minimum 3.3V boost

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