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DS26401N Datasheet(PDF) 98 Page - Dallas Semiconductor |
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DS26401N Datasheet(HTML) 98 Page - Dallas Semiconductor |
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98 / 309 page  DS26401 Octal T1/E1/J1 Framer 98 Register Name: RIM5 Register Description: Receive Interrupt Mask 5 (HDLC) Register Address: 0A4h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 Bit # 7 6 5 4 3 2 1 0 Name — — ROVR RHOBT RPE RPS RHWMS RNES Default 0 0 0 0 0 0 0 0 Bit 0 / Receive-FIFO Not Empty Set Event (RNES) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Receive-FIFO Above High-Watermark Set Event (RHWMS) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Receive-Packet-Start Event (RPS) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Receive-Packet-End Event (RPE) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Receive-HDLC Opening-Byte Event (RHOBT) 0 = interrupt masked 1 = interrupt enabled Bit 5 / Receive-FIFO Overrun (ROVR) 0 = interrupt masked 1 = interrupt enabled Bits 6, 7 / Unused. Must be set = 0 for proper operation. |
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