LM2657MTC datasheet(3/26 Pages) NSC

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Pin Description (Continued)

with no intervening vias between this capacitor and the

DD/SGND pins. If the voltage on Pin 5 falls below the lower

UVLO threshold, the upper and lower FETs are both turned

OFF. ‘Power Not Good’ is also signaled immediately (on Pin

9.) Normal operation will resume once the fault condition has

cleared. Additionally if the voltage on this pin falls below the

minimum voltage required for logic operation (about 1.8V

typ) the part will shutdown identically to enable (see pin 8)

being pulled low.

Pin 6, FREQ: Frequency adjust pin. The switching frequency

(for both channels) is set by a resistor connected between

this pin and ground. A value of 22.1k

Ω sets the frequency to

300kHz (nominal). If the resistance is increased, the switch-

ing frequency falls. An approximate relationship is that for

every 7.3k

Ω increase (or decrease) in the value of the fre-

quency adjust resistance, the time period (1/f) increases (or

decreases) by about 1µs.

Pin 7, SGND: Signal Ground pin. This is the lower rail for the

control and logic sections of both channels. SGND should be

connected on the PCB to the system ground, which in turn is

connected to PGND1 and PGND2. The layout is important

and the recommendations in the section Layout Guidelines

should be followed.

Pin 8, EN: IC Enable pin. When EN is taken high, both

channels are enabled by means of a Soft-start power-up

sequence (see Pin 4). When EN is brought low, ‘Power Not

Good’ is signaled within 100ns. The Soft-start capacitor is

then discharged by an internal 1.8k

Ω resistor (R

SS_DCHG,

see Electrical Characteristics table) to ground.

Pin 9, PGOOD: Power Good output pin. An open-Drain logic

output that is pulled high with an external pull-up resistor,

indicating that both output voltages are within a pre-defined

‘Power Good’ window, V

IN and VDD are within required op-

erating range, and enable is high. Outside this window, this

pin is internally pulled low (‘Power Not Good’ signaled) pro-

vided the output error lasts for more than 7µs. The pin also

goes low within 100ns of the Enable pin being taken low, or

DD going below UVLO, or VIN going below UVLO irrespec-

tive of the output voltage level. Regulation on both channels

must be achieved first before fault monitoring becomes ac-

tive (i.e. PGOOD must have been high prior to occurrence of

the fault condition for a fault to be asserted). For correct

signaling on this pin under single-channel operation, see

description of Pin 2.

Pin 10, FPWM: Logic input for selecting either the Forced

PWM (‘FPWM’) Mode or Pulse-skip Mode (‘SKIP’) for both

channels (together). When the pin is driven high, the IC

operates in the FPWM mode, and when pulled low or left

floating, the SKIP mode is enabled. In FPWM mode, the

lower FET of a given channel is always ON whenever the

upper FET is OFF (except for a narrow shoot-through pro-

tection deadband). This leads to continuous conduction

mode of operation, which has a fixed frequency and (almost)

fixed duty cycle down to very light loads. But this does

reduce efficiency at light loads. The alternative is the SKIP

mode, where the lower FET remains ON only till the voltage

on the Switch pin (see Pin 27 or Pin 16) goes above -2.2mV

(typical). So for example, for a 21m

Ω FET, this translates to

a current threshold of 2.2/21 = 0.1A. Therefore if the (instan-

taneous) inductor current falls below this value, the lower

FET will turn OFF every cycle at this point (when operated in

SKIP mode). This threshold is set by the ‘Zero-cross Com-

parator’ in the Block Diagram. Note that if the inductor cur-

rent waveform is high enough to cause the SW pin to be

always below this ‘zero-cross threshold’ (see Electrical Char-

acteristics table), there will be no observable difference be-

tween FPWM and SKIP mode settings (in steady-state).

SKIP mode, when it occurs, is clearly a discontinuous mode

of operation. However, in conventional discontinuous mode,

the duty cycle keeps falling (towards zero) as the load de-

creases. But the LM2657 does not ‘allow’ the duty cycle to

fall by more than 15% of its original value (at the CCM-DCM

boundary). This leads to pulse-skipping, and so the average

frequency decreases as the load decreases. This mode of

operation improves efficiency at light loads, but the fre-

quency is effectively no longer a constant. Note that a mini-

mum preload of 0.1mA should be maintained on the output

of each channel to ensure regulation in SKIP mode. The

resistive divider from output to ground used to set the output

voltage could be designed to serve as this preload.

Pin 11, SS2: Soft-start pin for Channel 2. See Pin 4.

Pin 12, COMP2: Compensation pin for Channel 2. See Pin

Pin 13, FB2: Feedback pin for Channel 2. See Pin 2.

Pin 14, SENSE2: Output voltage sense pin for Channel 2.

See Pin 1.

Pin 15, ILIM2: Channel 2 Current Limit pin. When the bottom

FET is ON, a 62µA (typical) current flows out of this pin into

an external current limit setting resistor connected to the

drain of the lower FET. This is a current source so the drop

across this resistor tries to push the voltage on this pin to a

more positive value. However, the drain of the lower FET,

which is connected to the other side of the same resistor, is

trying to go more negative as the load current increases.

Therefore at some value of current, the voltage on this pin

will cross zero and start to go negative. This is the current

limiting condition and it is detected by the ‘Current Limit

Comparator’ seen in the Block Diagram. When a current limit

condition has been detected, the next ON-pulse of the upper

FET will be omitted. The lower FET will again be monitored

to determine if the current has fallen below the threshold. If it

has, the next ON-pulse will be permitted. If not, the upper

FET will stay OFF, and remain so for several cycles if nec-

essary, until the current returns to normal. Eventually, if the

overcurrent condition persists and the upper FET has not

been turned ON, the output will start to fall eventually trig-

gering “Power not Good”.

Pin 16, SW2: The Switching node of the buck regulator of

Channel 2. Also serves as the lower rail of the floating driver

of the upper FET.

Pin 17, HDRV2: Gate drive pin for the upper FET of Channel

2 (High-side drive). The top gate driver is interlocked with the

bottom

gate

driver

prevent

shoot-through/cross-

conduction.

Pin 18, BOOT2: Bootstrap pin for Channel 2. This is the

upper supply rail for the floating driver of the upper FET. It is

bootstrapped by means of a ceramic capacitor connected to

the channel Switching node. This capacitor is charged up by

the IC to a value of about 5V as derived from the V5 pin (Pin

21).

Pin 19, PGND2: Power Ground pin of Channel 2. This is the

return path for the bottom FET gate drive. Both the PGND’s

are to be connected on the PCB to the system ground and

also to the Signal ground (Pin 7) in accordance with the

recommended Layout Guidelines .

Pin 20, LDRV2: Gate drive pin for the Channel 2 bottom FET

(Low-side drive). The bottom gate driver is interlocked with

the

top

gate

driver

prevent

shoot-through/cross-

conduction.

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