LM2715 datasheet(16/20 Pages) NSC

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Operation (Continued)

exceed the switch current limit. Using Schottky diodes with

lower forward voltage drop will decrease power dissipation

and increase efficiency.

DC GAIN AND OPEN-LOOP GAIN

Since the control stage of the converter forms a complete

feedback loop with the power components, it forms a closed-

loop system that must be stabilized to avoid positive feed-

back and instability. A value for open-loop DC gain will be

required, from which you can calculate, or place, poles and

zeros to determine the crossover frequency and the phase

margin. A high phase margin (greater than 45˚) is desired for

the best stability and transient response. For the purpose of

stabilizing the LM2715, choosing a crossover point well be-

low where the right half plane zero is located will ensure

sufficient phase margin. A discussion of the right half plane

zero and checking the crossover using the DC gain will

follow.

INPUT AND OUTPUT CAPACITOR SELECTION

The switching action of a boost regulator causes a triangular

voltage waveform at the input. A capacitor is required to

reduce the input ripple and noise for proper operation of the

regulator. The size used depends on the application and

board layout. If the regulator will be loaded uniformly, with

very little load changes, and at lower current outputs, the

input capacitor size can often be reduced. The size can also

be reduced if the input of the regulator is very close to the

source output. The size will generally need to be larger for

applications where the regulator is supplying nearly the

maximum rated output or if large load steps are expected. A

minimum value of 10µF should be used for the less stressful

conditions while a 22µF to 47µF capacitor may be required

for higher power and dynamic loads. Larger values and/or

lower ESR may be needed if the application requires very

low ripple on the input source voltage.

The choice of output capacitors is also somewhat arbitrary

and depends on the design requirements for output voltage

ripple. It is recommended that low ESR (Equivalent Series

Resistance, denoted R

ESR) capacitors be used such as

ceramic, polymer electrolytic, or low ESR tantalum. Higher

ESR capacitors may be used but will require more compen-

sation which will be explained later on in the section. The

ESR is also important because it determines the peak to

peak output voltage ripple according to the approximate

equation:

∆V

OUT

) 2

∆i

LRESR (in Volts)

A minimum value of 10µF is recommended and may be

increased to a larger value. After choosing the output capaci-

tor you can determine a pole-zero pair introduced into the

control loop by the following equations:

Where R

L is the minimum load resistance corresponding to

the maximum load current. The zero created by the ESR of

the output capacitor is generally very high frequency if the

ESR is small. If low ESR capacitors are used it can be

neglected. If higher ESR capacitors are used see the High

Output Capacitor ESR Compensation section.

RIGHT HALF PLANE ZERO

A current mode control boost regulator has an inherent right

half plane zero (RHP zero). This zero has the effect of a zero

in the gain plot, causing an imposed +20dB/decade on the

rolloff, but has the effect of a pole in the phase, subtracting

another 90˚ in the phase plot. This can cause undesirable

effects if the control loop is influenced by this zero. To ensure

the RHP zero does not cause instability issues, the control

loop should be designed to have a bandwidth of less than

1/6 the frequency of the RHP zero. This zero occurs at a

frequency of:

where I

LOAD is the maximum load current.

SELECTING THE COMPENSATION COMPONENTS

The first step in selecting the compensation components R

and C

C is to set a dominant low frequency pole in the control

loop. Simply choose values for R

C and CC within the ranges

given in the Introduction to Compensation section to set this

pole in the area of 10Hz to 500Hz. The frequency of the pole

created is determined by the equation:

where R

O is the output impedance of the error amplifier,

approximately 1M

Ω. Since R

C is generally much less than

O, it does not have much effect on the above equation and

can be neglected until a value is chosen to set the zero f

ZC.

ZC is created to cancel out the pole created by the output

capacitor, f

P1. The output capacitor pole will shift with differ-

ent load currents as shown by the equation, so setting the

zero is not exact. Determine the range of f

P1 over the ex-

pected loads and then set the zero f

ZC to a point approxi-

mately in the middle. The frequency of this zero is deter-

mined by:

Now R

C can be chosen with the selected value for CC.

Check to make sure that the pole f

PC is still in the 10Hz to

500Hz range, change each value slightly if needed to ensure

both component values are in the recommended range. After

checking the design at the end of this section, these values

can be changed a little more to optimize performance if

desired. This is best done in the lab on a bench, checking the

load step response with different values until the ringing and

overshoot on the output voltage at the edge of the load steps

is minimal. This should produce a stable, high performance

circuit. For improved transient response, higher values of R

should be chosen. This will improve the overall bandwidth

which makes the regulator respond more quickly to tran-

sients. If more detail is required, or the most optimal perfor-

mance is desired, refer to a more in depth discussion of

compensating current mode DC/DC switching regulators.

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