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HT45F4MA Datasheet(PDF) 39 Page - Holtek Semiconductor Inc |
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HT45F4MA Datasheet(HTML) 39 Page - Holtek Semiconductor Inc |
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39 / 145 page  Rev. 1.20 38 De�e��e� 1�� 201� Rev. 1.20 39 De�e��e� 1�� 201� HT45F4MA/HT45FH4MA/HT45FH4MA-1 Power Bank Flash MCU HT45F4MA/HT45FH4MA/HT45FH4MA-1 Power Bank Flash MCU Control Register TheSMODregisterisusedtocontroltheinternalclockswithinthedevice. SMOD Register Bit 7 6 5 4 3 2 1 0 Na�e CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 1 1 0 — 0 0 1 0 Bit7~5 CKS2 ~ CKS0:ThesystemclockselectionwhenHLCLKis“0” 000:fSUB 001:fSUB 010:fH/64 011:fH/32 100:fH/16 101:fH/8 110:fH/4 111:fH/2 Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.In additiontothesystemclocksource,whichcanbeLIRC,adividedversionofthehigh speedsystemoscillatorcanalsobechosenasthesystemclocksource. Bit4 Unimplemented,readas"0" Bit3 LTO:LIRCSystemOSCSSTreadyflag 0:Notready 1:Ready ThisisthelowspeedsystemoscillatorSSTreadyflagwhichindicateswhenthelow speedsystemoscillatorisstableafterpoweronresetorawake-uphasoccurred.The flagwillchangetoahighlevelafter1~2cycles. Bit2 HTO:HIRCSystemOSCSSTreadyflag 0:Notready 1:Ready ThisisthehighspeedsystemoscillatorSSTreadyflagwhichindicateswhenthehigh speedsystemoscillatorisstableafterawake-uphasoccurred.Thisflagisclearedto “0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafter thehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1” bytheapplicationprogramafterdevicepower-on.Theflagwillbelowwheninthe SLEEPorIDLE0Modebutafterpoweronresetorawake-uphasoccurred,theflag willchangetoahighlevelafter15~16clockcyclesiftheHIRCoscillatorisused. Bit1 IDLEN:IDLEModeControl 0:Disable 1:Enable ThisistheIDLEModeControlbitanddetermineswhathappenswhentheHALT instructionisexecuted.Ifthisbitishigh,whenaHALTinstructionisexecutedthe devicewillentertheIDLEMode.IntheIDLE1ModetheCPUwillstoprunning butthesystemclockwillcontinuetokeeptheperipheralfunctionsoperational,if FSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstop inIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALT instructionisexecuted. Bit0 HLCLK:SystemClockSelection 0:fH/2~fH/64orfSUB 1:fH ThisbitisusedtoselectifthefHclockorthefH/2~fH/64orfSUBclockisusedasthe systemclock.WhenthebitishighthefHclockwillbeselectedandiflowthefH/2~ fH/64orfSUBclockwillbeselected.WhensystemclockswitchesfromthefHclockto thefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconservepower. |
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