VIPER15LD datasheet(30/40 Pages) STMICROELECTRONICS

30 / 40 page

Operation description

VIPER15

30/40

Doc ID 15455 Rev 5

Equation 11

The RFB(DYN) is the dynamic resistance seen by the FB pin and reported on Table 8 on

page 8

The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB. The

Equation 8 on page 29

can be still used to calculate the OLP delay time but CFB1 has to be

considered instead of CFB. Using the alternative compensation network, the designer can

satisfy, in all case, the loop stability and the enough OLP delay time alike.

Figure 34.

FB pin configuration (option 1)

Figure 35.

FB pin configuration (option 2)

()

)

DYN

(

PFB

⋅

From sense FET

4.8V

BURST

PWM

CONTROL

Cfb

To PWM Logic

BURST-MODE

REFERENCES

BURST-MODE

LOGIC

PWM

OLP comparator

To disable logic

4.8V

From sense FET

PWM

CONTROL

PWM

BURST

To disable logic

OLP comparator

To PWM Logic

BURST-MODE

LOGIC

Cfb1

Rfb1

Cfb

BURST-MODE

REFERENCES

Obsolete

Product(s)

- Obsolete

Product(s)

VIPER15LD Datasheet(PDF) 30 Page - STMicroelectronics

VIPER15LD Datasheet(HTML) 30 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL