M0516ZDN datasheet(9/86 Pages) ETC2

9 / 86 page

M051 DN/DE

Oct. 05, 2015

Page 9 of 86

Rev 1.03

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Multiple clock sources



Supports wake-up from Power-down or Sleep mode

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Interrupt or reset selectable on watchdog time-out

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Time-out reset delay period time can be selected



WWDT (Window Watchdog Timer)



6-bit down counter with 11-bit pre-scale for wide range window selected



PWM



Up to four built-in 16-bit PWM generators, providing eight PWM outputs or four

complementary paired PWM outputs

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Individual clock source, clock divider, 8-bit pre-scalar and dead-zone generator for

each PWM generator

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PWM interrupt synchronized to PWM period



16-bit digital Capture timers with rising/falling capture inputs



Supports capture interrupt

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Internal 10 kHz to PWM clock source

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Polar inverse function

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Center-aligned type function

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Timer duty interrupt enable function

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Two kinds of PWM interrupt period/duty type selection

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Period/duty trigger ADC function

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PWM Timer synchronous start function



UART

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Up to two sets of UART devices

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Programmable baud-rate generator

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Buffered receiver and transmitter, each with 15 bytes FIFO

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Optional flow control function (CTS and RTS)

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Supports IrDA(SIR) function

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Supports RS485 function

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Supports LIN function



SPI

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Up to two sets of SPI devices

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Supports Master/Slave mode

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Full-duplex synchronous serial data transfer

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Provides 3 wire function

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Variable length of transfer data from 1 to 32 bits

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MSB or LSB first data transfer

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Rx latching data can be either at rising edge or at falling edge of serial clock

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Tx sending data can be either at rising edge or at falling edge of serial clock

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Supports Byte Suspend mode in 32-bit transmission



PLL clock source



4-level depth FIFO buffer for better performance and flexibility in SPI Burst Transfer

mode

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