N571P032 Data Sheet

Release Date: January, 2015

Version 1.4

- 9 -

5. Typical Application Circuit

The followings are for general reference.

1.

Crystal is optional, it is for RTC timer or for the reference clock of internal PLL. XI_32K

and XO_32K are no connection for the application without crystal oscillator.

2.

PLL is optional, it works with crystal oscillation to support higher accuracy system clock.

PLLC is no connection for the application does not use PLL.

3.

Do not make VDDSPI spare, it has to connect to LDO33 (Voutx) or connect to VDDIO

based on application

’s request even if GPA0~4 (share with SPI interface) are spare.

4.

Bypass cap is must for LDO33 (Voutx) to support chip core power even if the

application does not use LDO33 to drive external device.

5.

Bypass cap is must for AVDD, the power output pad of internal 3V LDO specific for

ADC/PGC part, it can use a smaller cap if the application does not use ADC/PGC.

6.

For 2-battery (2*1.5V) and 3-battery (3*1.5V), the application circuits can be the same,

but connecting VDDSPI to VDDIO can gain higher voltage for 2-battery application with

SPI-Flash.

5.1 Playback

DI0

CLK0

/HOLD0

VDDSPI

VSSIOA

DO0

/CS0

/WP0

VOUTX or VDDIOA

+

47u

0.1u

SPI Flash

DO

2

GND

4

CLK

6

VCC

8

/CS

1

/WP

3

DI

5

/HOLD

7

0.1u

6.8K

4.7u

3300 p

0.1u

N571P032

GPA3/MISO0

VDDSPI

VDDIOA/VDDIO1

GPA12/ADC4

GPA13/ADC5

GPA14/MIC_BIAS

TEST

XI_32K (X32I)

VDDIOB/VDDIO2

GPB5/ICE_TDA

VDDSPK

VSSSPK

VPP

GPA1/SSB00

GPA4/MOSI0

VOUTX/LDO33

VSSIOA/VSSIO1

AVSS

GPA15/PGCVREF

AVDD

RSTB

XO_32K (X32O)

VSSIOB/VSSIO2

GPB4/ICE_TCK

SPKP

SPKN

VMID

GPA2/SPCK0

BATTERY

+

10u

1

2

32.768K

0.1u

0.1u

15p

15p

FB

FB

0.1u

1u (option)

VSS

GND

GND

GND

VSS

GND

GND

VCC

VCC

For PLL (option)

SPI Flash (option)

Crystal (option)

For RTC, PLL

OTP-WRITER Interface

Nu-Link ICE Interface

Speaker

GND