CS43199 datasheet(86/111 Pages) CIRRUS

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DS1113F1

CS4399

7.5 Analog Output and PCM Registers

0MIX_PCM_

DSD

Enable PCM stream mixing into DSD stream. This bit must be set only after MIX_PCM_PREP is enabled. Disable this

bit prior to disabling MIX_PCM_PREP bit. This mode requires DSD_EN to be enabled and DSD_PRC_SRC set to

receive DSD through either the DSD interface or XSP.

0 (Default) Function disabled

1 Enable PCM stream mixing into the DSD stream

7.4.7

DSD Processor Path Signal Control 3

Address 0x70006

R/W

76543210

DSD_ZERODB DSD_HPF_EN

—

SIGCTL_

DSDEQPCM

DSD_INV_A

DSD_INV_B

DSD_SWAP_

CHAN

DSD_COPY_

CHAN

Default

01000000

Bits

Name

Description

7DSD_

ZERODB

Setting on DSD stream volume to match PCM stream volume.

0 (Default) The SACD +3.1-dB level (71% modulation index) matches PCM 0 dB full scale.

1 The SACD 0-dB reference level (50% modulation index) matches PCM 0 dB full scale.

DSD_HPF_EN Enable the high pass filter in the DSD processor.

0 HPF disabled

1 (Default) Enable HPF in the DSD processor

5—

Reserved

4SIGCTL_

DSDEQPCM

Enable DSD signal path control register bits to be controlled by PCM setting. DSD setting is ignored. Register bits

affected are the following:

DSD_VOL_BEQA, DSD_SZC, DSD_AMUTE, DSD_AMUTE_BEQA, DSD_MUTE_A, DSD_MUTE_B, DSD_INV_A,

DSD_INV_B, DSD_SWAP_CHAN, DSD_COPY_CHAN

After set, each DSD_x register bit is equal to setting of PCM_x register bit.

0 (Default) Function is disabled

1 Function is enabled

DSD_INV_A DSD Processor Channel A signal invert.

0 (Default) Function is disabled

1 Signal polarity of channel A is inverted

DSD_INV_B DSD Processor Channel B signal invert

0 (Default) the function is disabled

1 Signal polarity of channel B is inverted

DSD_SWAP_

CHAN

Swap channels A and B at the input. This bit takes effect before DSD_COPY_CHAN and DSD_INV_x.

0 (Default) Function disabled

1 Enable channel A and B swapping

0DSD_COPY_

CHAN

Copy channel A to channel B. This bit takes effect after DSD_SWAP_CHAN, but before DSD_INV_x.

0 (Default) Function disabled

1 Enable copy A to B function

7.5.1

Analog Output Control 1

Address 0x80000

R/W

76543210

——

OUT_FS

—

Default

00110000

Bits

Name

Description

7:6

—

Reserved

5:4

OUT_FS

Output full scale setting. This setting must only be updated when PDN_HP is set.

00 Reserved

01 Reserved

10 1.41 V

11 (Default) 1.73 V

3—

Reserved

2:0

—

Reserved

Bits

Name

Description

CS43199 Datasheet(PDF) 86 Page - Cirrus Logic

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