AM24LC21 datasheet(7/13 Pages) ETC

7 / 13 page

AM24LC21

Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM

(Preliminary)

Anachip Corp.

www.anachip.com.tw

Rev 0.0 Aug 10, 2002

7/13

SCL

SDA

(A)

(C)

(D)

(B)

(A)

START

Condition

Address or

acknowledge

valid

Data allowed to change

STOP

condition

Figure 3-3. Data transfer sequence on the serial bus

3.1.4 Data Valid (D)

The state of the data line represents valid data

when, after a START condition, the data line is

stable for the duration of the HIGH period of the

clock signal. The data on the line must be changed

during the LOW period of the clock signal. There is

one clock pulse per bit of data. Each data transfer

is initiated with a START condition and terminated

with a STOP condition. The number of the data

bytes transferred between the START and STOP

conditions is determined by the master device and

is theoretically unlimited, although only the last

eight will be stored when doing a write operation.

When an overwrite does occur it will replace data in

a first in first out fashion.

3.1.5 Acknowledge

Each receiving device, when addressed, is obliged

to generate an acknowledge after the reception of

each byte. The master device must generate an

extra clock pulse which is associated with this

acknowledge bit.

Note:

The

AM24LC21

does

not

generate

any

acknowledge bits if an internal programming cycle

is in progress.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in

such a way that the SDA line is stable LOW during

the HIGH period of the acknowledge related clock

pulse. Of course, setup and hold times must be

taken into account. A master must signal an end of

data to the slave by not generating an acknowledge

bit on the last byte that has been clocked out of the

slave. In this case, the slave must leave the data

line HIGH to enable the master to generate the

STOP condition.

SCL

SDA

START

STOP

SU:STO

HYS

HD:STA

SU:STA

Figure 3-4. Bus timing start/stop

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