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RF Monolithics, Inc.

Phone: (972) 233-290

Fax: (972) 387-8148

E-mail: info@rfm.com

RFM Europe

Phone: 44 1963 251383

Fax: 44 1963 251510

http://www.rfm.com

IC1003-050103

©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.

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RF Uart IC1003

Note that the ASH radio RX Data output signal is inverted before

being applied to the IC1003. The steady high pulse that begins

the start-of-data pulse sequence to the IC1003 is generated by

the reception of an eight-bit long RF transmission. This pulse

also helps "train" the base-band coupling capacitor in the ASH

radio for best data slicer noise rejection. The host processor

should generate inverted data for transmission by the ASH radio

and should input the same inverted data that drives the IC1003.

Data Encoding

Data should be encoded to provide frequent logic state

transitions (edges) to facilitate data clock alignment, and should

exhibit good dynamic DC-balance (50% high bits and 50% low

bits over any interval of 16 bits or less) to maintain the radio's

base-band capacitor training for best noise performance. The

popular encoding method is byte-to-12 bit symbolizing, which

encodes each byte as a pattern of 12 bits, always with six one

bits and six zero bits. Symbolizing requires fewer bits than

Manchester to encode a message, and also provides frequent

state transitions and good DC-balance. An example of 12-bit

symbolizing can be found in page 4.

Note that the IC1003 has no provisions for detecting end-of-

data. This provides flexibility in message length and data

encoding, but requires the message length and/or an end-of-

data symbol to be embedded in the data by the user and Start

Symbol Reset brought high will clear Start Symbol Detect.

Operation

A typical IC1003 application the RX Data output from the 2nd

generation ASH transceiver (or receiver) is applied to the IC1003.

In receive mode the IC1003 detects the presence of a specific

unique Start Symbol sequence and outputs a Start Detect. The

IC1003 generates data clocking (data valid) and shifts the data into

a 12 bit shift register and will rise the data Ready pin when a

Symbol is ready to be read. After the packet is received the Start

Detect Signal must be reset by Start Detect reset pin going high.

The IC1003 used as an transmitter interface will write in a 12 bit

symbol and while TX Enable is high will shift out the data out the

data out pin at the Clock Frequency dived by 40(40Mhz clock will

obtain a 1Mbps data rate). The IC1003 supports data rates from

100K – 1000K bits per second (bps)..

The IC1003 is implemented in an industrial temperature range

of

to the latest revision of Xilinx data sheet for detailed electrical and

mechanical specifications.

Start-of-Data Pulse Sequence Generation

The IC1003 start-of-data pulse sequence is a steady High pulse of

eight bit periods, followed by a sequence of eight bits in an

alternating high-low-high-low… pattern. This pulse sequence is

very unlikely to occur in a stream of white noise (data sliced),

providing good false triggering performance. The IC1003 outputs

the Start Detect pulse when the RX Data input line to the IC1003

has remained a steady low for eight bit periods. After eight bit

periods of a steady high, the data input should begin the eight-bit

sequence of alternating high and low bits. The eight-bit alternating

high-low sequence provides data clocking alignment training under

low signal-to-noise conditions (data edge jitter) and should be used

for best results.