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ICS91718 Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICS91718 Datasheet(HTML) 8 Page - Integrated Circuit Systems |
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8 / 11 page ![]() 8 ICS91718 0500D—07/15/04 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. AC Electrical Characteristics TA = 0 - 70°C; Supply Voltage VDD = 3.3 V ±0.3V PARAMETER DESCRIPTION TEST CONDITION MIN TYP MAX UNITS FIN Input Frequency Input Clock 14.318 80 MHz fOUT Output Frequency Spread Off 14.318 80 MHz tR Output Rise Time 15 pF load, 0.8V - 2.4V 0.5 1 ns tF Output Fall Time 15 pF load, 2.4 - 0.8V 0.5 1 ns IOD Output Duty Cycle 15 pf load 45 55 % tID Input Duty Cycle 45 55 % tJCYC Jitter, Cycle-to-Cycle 250 ps Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V Voltage on any pin with respect to GND . . . . -0.5 to +7.0 V Storage Temperature . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Operating Temperature . . . . . . . . . . . . . . . . . . 0°C to +85°C Ambient Operating Temperature under Bias . -55 to +125 °C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 0.5 W Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 85°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage VIH 2VDD + 0.3 V Input Low Voltage VIL VSS - 0.3 0.8 V Input High Current IIH VIN = VDD -5 5 µA Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 µA fIN = 14.318MHz 27 35 mA fIN = 66.66MHz 42 50 mA Powerdown Current IDD3.3PD 35 mA Pin Inductance Lpin 7nH CIN Logic Inputs 5 pF COUT Output pin capacitance 6 pF Transition time 1 Ttrans To 1st crossing of target frequency 3 ms Settling time 1 Ts From 1st crossing to 1% target frequency 3 ms Clk Stabilization 1 TSTAB From VDD = 3.3 V to 1% target frequency 1 3 ms Delay 1 tPZH,tPZL Output enable delay (all outputs) 1 10 ns 1Guaranteed by design, not 100% tested in production. Pin Capacitance 1 Supply Current IDD |
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