RT8128CGSP datasheet(13/15 Pages) RICHTEK

13 / 15 page

RT8128A/C

DS8128A/C-03

March 2016

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

PEAK

SOAR

OUT

) x L

2 x C

x V



where IPEAK is the peak inductor current.

Output Capacitor Stability

Stability is determined by the value of the ESR zero relative

to the switching frequency. The point of instability is given

by the following equation :



 SW

ESR

OUT

2 x

x ESR x C

Do not put high value ceramic capacitors directly across

the outputs without taking precautions to ensure stability.

Large ceramic capacitors can have a high ESR zero

frequency and cause erratic, unstable operation. However,

it is easy to add enough series resistance by placing the

capacitors a couple of inches downstream from the

inductor and connecting VOUT or the FB voltage-divider

close to the inductor.

Unstable operation manifests itself in two related and

distinctly different ways : double-pulsing and feedback loop

instability.

Double-pulsing occurs due to noise on the output or

because the ESR is so low that there is not enough voltage

ramp in the output voltage signal. This

“fools” the error

comparator into triggering a new cycle immediately after

the 400ns minimum off-time period has expired. Double

pulsing is more annoying than harmful, resulting in nothing

worse than increased output ripple. However, it may

indicate the possible presence of loop instability, which

is caused by insufficient ESR.

Loop instability can result in oscillations at the output in

the form of line or load perturbations, which can trip the

over-voltage protection latch or cause the output voltage

to fall below the tolerance limit.

The easiest method for checking stability is to apply a

very fast zero-to-max load transient and carefully observe

the output-voltage-ripple envelope for overshoot and ringing.

It helps to simultaneously monitor the inductor current

with an AC current probe. Do not allow more than one

cycle of ringing after the initial step-response under- or

over-shoot.

MOSFET Selection

The majority of power loss in the step-down power

conversion is due to the loss in the power MOSFETs. For

low voltage high current applications, the duty cycle of

the high-side MOSFET is small. Therefore, the switching

loss of the high-side MOSFET is of concern. Power

MOSFETs with lower total gate charge are preferred in

such kind of application. However, the small duty cycle

means the low-side MOSFET is on for most of the

switching cycle. Therefore, the conduction loss tends to

dominate the total power loss of the converter. To improve

the overall efficiency, MOSFETs with low RDS(ON) are

preferred in the circuit design. In some cases, more than

one MOSFET are connected in parallel to further decrease

the on-state resistance. However, this depends on the

low-side MOSFET driver capability and the budget.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the ambient temperature, and

θJAis the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

SOP-8 (Exposed Pad) package, the thermal resistance,

θJA, is 30.6°C/W on the standard JEDEC 51-7 four-layers

thermal test board. The maximum power dissipation at

TA = 25

°C can be calculated by the following formula :

PD(MAX) = (125

°C − 25°C) / (30.6°C/W) = 3.26W for

SOP-8 (Exposed Pad) package

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