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Low Voltage PLL Clock Driver

The MPC958 is a 3.3V compatible, PLL based clock driver device

targeted for high performance clock tree designs. With output frequencies

of up to 200MHz and output skews of 200ps the MPC958 is ideal for the

most demanding clock tree designs. The devices employ a fully

differential PLL design to minimize cycle–to–cycle and phase jitter.

The MPC958 has a differential LVPECL reference input along with an

external feedback input. These features make the MPC958 ideal for use

as a zero delay, low skew fanout buffer. The device performance has

been tuned and optimized for zero delay performance. The MR/OE input

pin will tristate the output buffers when driven “high”.

The MPC958 is fully 3.3V compatible and requires no external loop

filter components. All control inputs accept LVCMOS or LVTTL

compatible levels while the outputs provide LVCMOS levels with the

ability to drive terminated 50

Ω transmission lines. For series terminated

50

Ω lines, each of the MPC958 outputs can drive two traces giving the

device an effective fanout of 1:22. The device is packaged in a 7x7mm

32–lead LQFP package to provide the optimum combination of board

density and performance.

Figure 1. Logic Diagram

PECL_CLK

PECL_CLK

FB_CLK

Phase

Detector

LPF

VCO

200–400MHz

÷2

VCO_SEL

BYPASS

QFB

Q0:8

Q9

9

÷2

MR/OE

PLL_EN

0

1

0

1

0

1

(Int pull up)

(Int pull down)

(Int pull up)

(Int pull up)

(Int pull up)

(Int pull down)

(Int pull up)

MPC958

LOW VOLTAGE

PLL CLOCK DRIVER

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A–02

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com