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Figure 5. This FFT was measured with the MAX104 undersampling an analog input frequency of 1GHz at

a sampling rate of 1Gsps.

Similar to its analog input structure, the MAX104 features clock inputs designed for either single-ended or

differential operation with very flexible input-drive requirements. Each clock input is terminated with an

on-chip, laser-trimmed, 50

W precision NiCr resistor to the clock-termination return. This termination may

be connected anywhere between ground and -2V for compatibility with standard emitter-coupled-logic

(ECL) drive levels.

The clock inputs are internally buffered with an amplifier to ensure proper operation of the ADC even with

small-amplitude sine-wave sources. The MAX104 was designed for single-ended operation, maintaining

superior dynamic performance when using low-phase-noise sine-wave clock input signals with as little as

100mV amplitude.

To obtain the lowest jitter clock drive, a low-phase-noise sine-wave source can be AC- or DC-coupled into

a single clock input. The MAX104 can accommodate clock amplitudes up to 1V (2V peak-to-peak) with

the clock-termination return connected to ground. The dynamic performance of the ADC is essentially

unaffected by clock signal amplitudes from 100mV to 1V.

The ADC can be driven from a standard differential ECL clock source by simply setting the clock-

termination voltage to -2V. To maintain the best performance, a very- high-speed differential ECL driver

should be used.

Clock inputs CLK+ and CLK- may also be driven with positive referenced ECL (PECL) logic levels if the

clock inputs are AC coupled. A single-ended ECL drive can also be used if the undriven clock input is

connected to the ECL VTT voltage (nominally -1.3V).

Another useful feature of the MAX104 may be its internal output demultiplexer (demux) circuitry. This

circuitry provides three different modes of operation. The demux operation is controlled by two transistor-

transistor-logic (TTL)/complementary-metal-oxide-semiconductor (CMOS)-compatible digital inputs:

DEMUXEN, which activates or deactivates the internal demux, and DIVSELECT, which selects one of

three demux modes (DIV1, DIV2, or DIV4).

The DIV2 (demux) mode reduces the output data rate to one-half the sample clock rate. The demuxed

outputs are presented in dual 8-bit format with two consecutive samples in the primary and auxiliary output