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SL74HC652 Datasheet(PDF) 4 Page - System Logic Semiconductor

Part # SL74HC652
Description  Octal 3-State Bus Transceivers and D Flip-Flops
PDF  9 Pages
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Manufacturer  SLS [System Logic Semiconductor]
Direct Link  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL74HC652 Datasheet(HTML) 4 Page - System Logic Semiconductor

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SL74HC652
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to
-55
°C
≤85°C
≤125°C
Unit
tPLH, tPHL
Maximum Propagation Delay, Input A to Output B
(or Input B to Output A)
(Figures 2,3 and 9)
2.0
4.5
6.0
180
36
31
225
45
38
270
54
46
ns
tPLH, tPHL
Maximum Propagation Delay, A-to-B Clock to
Output B (or B-to-A Clock to Output A)
(Figures 1 and 9)
2.0
4.5
6.0
240
48
41
300
60
51
360
72
61
ns
tPLH, tPHL
Maximum Propagation Delay, A-to-B Source to
Output B (or B-to-A Source to Output A) (Figures
4 and 9)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
tPLZ, tPHZ
Maximum Propagation Delay , Direction or Output
Enable to Output A or B
(Figures 5,6 and 10)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
tPZL, tPZH
Maximum Propagation Delay , Direction or Output
Enable to Output A or B
(Figures 5,6 and 10)
2.0
4.5
6.0
180
36
31
225
45
38
270
54
46
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output
(Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
COUT
Maximum Three-State I/O Capacitance
(Output in High-Impedance State
-
15
15
15
pF
Power Dissipation Capacitance (Per Channel)
Typical @25
°C,V
CC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC
2f+I
CCVCC
60
pF



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