ICS66203 datasheet(3/6 Pages) ETC

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HDTV Audio/Video Clock Source

MDS 662-03 C

Revision 082003

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ●

www.icst.com

ICS662-03

Application Information

Series Termination Resistor

Clock output traces should use series termination. To

series terminate a 50

Ω trace (a commonly used trace

impedance), place a 33

Ω resistor in series with the

clock line, as close to the clock output pin as possible.

The nominal impedance of the clock output is 20

Ω.

Decoupling Capacitors

As with any high performance mixed-signal IC, the

ICS662-03 must be isolated from system power supply

noise to perform optimally.

Decoupling capacitors of 0.01µF must be connected

between VDD (pin 2) and the PCB ground plane (pin

3).

PCB Layout Recommendations

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

1) Each 0.01µF decoupling capacitor should be

mounted on the component side of the board as close

to the VDD pin as possible. No vias should be used

between decoupling capacitor and VDD pin. The PCB

trace to VDD pin should be kept as short as possible,

as should the PCB trace to the ground via. Distance of

the ferrite bead and bulk decoupling from the device is

less critical.

2) To minimize EMI and obtain the best signal integrity,

the 33

Ω series termination resistor should be placed

close to the clock output.

3) An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers (the ferrite bead and bulk decoupling

capacitor can be mounted on the back). Other signal

traces should be routed away from the ICS662-03. This

includes signal traces just underneath the device, or on

layers adjacent to the ground plane layer used by the

device.

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