TPS2112

TPS2113

SLVS446 – DECEMBER 2002

www.ti.com

6

TRUTH TABLE

EN

VI(VSNS) > 0.8V

VI(IN2) > VI(IN1)

STAT

OUT(1)

Yes

X

0

IN1

0

No

No

0

IN1

0

No

Yes

Hi-Z

IN2

1

X

X

0

Hi-Z

(1)The under-voltage lockout circuit causes the output OUT to go Hi-Z if the

selected power supply does not exceed the IN1/IN2 UVLO, or if neither of

the supplies exceeds the internal VDD UVLO.

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

EN

2

I

EN is a TTL and CMOS compatible input with a 1-

µA pull-up. The truth table shown above illustrates the functionality of

EN.

GND

5

I

Ground

IN1

8

I

Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at

least one supply exceeds the internal VDD UVLO.

IN2

6

I

Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and

at least one supply exceeds the internal VDD UVLO.

ILIM

4

I

A resistor RILIM from ILIM to GND sets the current limit IL to 250/RILIM and 500/RILIM for the TPS2112 and TPS2113,

respectively.

OUT

7

O

Power switch output

STAT

1

O

STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is Hi-Z

(i.e., EN is equal to logic 0)

VSNS

3

I

An internal power FET connects OUT to IN1 if the VSNS voltage is greater than 0.8 V. Otherwise, the FET connects OUT

to the higher of IN1 and IN2. The truth table shown above illustrates the functionality of VSNS.