S5725 datasheet(13/31 Pages) SII

13 / 31 page

HIGH-SPEED BIPOLAR HALL EFFECT LATCH

Rev.2.5_01

S-5725 Series

2. 3 S-5725JxBxx

Table 14

(Ta =

+25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Test

Circuit

Power supply voltage

VDD

−

2.7

5.0

5.5

−

Current consumption

IDD

Average value

−

1400.0 2000.0

μA

Current consumption during

power-down

IDD2

VCE = VSS

−

μA

Output voltage

VOUT

Nch open-drain

output product

Output transistor Nch,

IOUT = 2 mA

−

0.4

CMOS output

product

Output transistor Nch,

IOUT = 2 mA

−

0.4

Output transistor Pch,

IOUT =

−2 mA

VDD

−

0.4

−

Leakage current

ILEAK

Nch open-drain output product

Output transistor Nch, VOUT = 5.5 V

−

μA

Awake mode time

tAW

−

μs

−

Sleep mode time

tSL

−

μs

−

Operating cycle

tCYCLE

tAW

+ tSL

−

100

μs

−

Enabling pin input voltage "L"

VCEL

−

VDD

0.3

−

Enabling pin input voltage "H"

VCEH

−

VDD

0.7

−

Enabling pin input current "L"

ICEL

VDD = 5.0 V, VCE = 0 V

−1

−

μA

Enabling pin input current "H"

ICEH

VDD = 5.0 V, VCE = 5.0 V

−1

−

μA

Power-down transition time

tOFF

−

100

μs

−

Enable transition time

tON

−

100

μs

−

Output logic update time after

inputting "H" to enabling pin

tOE

−

200

μs

−

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